參數(shù)資料
型號： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個10/100M以太網(wǎng)控制器
文件頁數(shù)： 31/92頁
文件大?。?/td> 2801K
代理商： IP100
IP100
10.2.8 TxFrameControl
Class............................. DMA Data Structures, TFD
Base Address ............... Start of TFD
Address Offset .............. 0x04
Access Mode ................ Read/Write
Width ............................ 32 bits
TxFrameControl contains frame control information for the transmit DMA function and the transmit function.
BIT
BIT NAME
1..0
WordAlign
Word Alignment. WordAlign determine the boundary to which transmit frame
lengths are rounded up in the transmit FIFO, and transmitted onto the network
medium.
BIT 1
BIT 0
0
0
1
0
x
1
When using word alignment, it is the responsibility of the host system to
recognize that any added bytes necessary to achieve the desired alignment
may affect byte oriented functions and fields (i.e. if the Ethernet Length/Type
field holds a frame length, this value is not updated to reflect any bytes added
via word alignment).
9..2
FrameId
Frame Identification. FrameId can be used as a frame ID or sequence number
and can be used by the host system (via the TxStatus register) to determine
frames which experienced errors.
12..10
Reserved
Reserved for future use.
13
FcsAppendDisable
FCS Append Disable. If FcsAppendDisable is a logic 1, the IP100 will not
append the 4-byte FCS to the end of each transmit frame. In this case, the
host system must supply the frame’s FCS as part of the data transferred via
transmit DMA. An exception exists when a transmit under run occurs; in this
case a guaranteed-bad FCS will be appended to the frame by the IP100.
When FcsAppendDisable is a logic 0, the IP100 will compute and append
FCS for each transmit frame.
14
Reserved
Reserved for future use.
15
TxIndicate
Transmit Indicate. If TxIndicate is a logic 1, the IP100 will issue a TxComplete
interrupt when transmission of the frame completes.
16
TxDMAComplete
Transmit DMA Complete. When TxDMAComplete is a logic 1, the frame
transfer by transmit DMA is complete. The IP100 sets TxDMAComplete to a
logic 1 after completing transfer via transmit DMA, all fragments specified in
the TFD.
30..17
Reserved
Reserved for future use.
31
TxDMAIndicate
Transmit DMA Indicate. If TxDMAIndicate is a logic 1, the IP100 will issue a
TxDMAComplete interrupt upon completion of transmit DMA for this frame.
The TFC is read twice by the IP100; the first time to write the TFC to the
transmit FIFO before frame data transfer, and again after the transmit DMA
operation is complete to test TxDMAIndicate in order to determine whether to
generate an interrupt. This dual read process allows the host system time to
change TxDMAIndicate while the transmit DMA transfer is in progress.
IP100-DS-R03
May 27, 2003
31/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT DESCRIPTION
ALIGNMENT
Align to Double Word
Align t o Word
Alignment Disabled
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