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| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 16/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
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IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
16/92
IP100-DS-R03
May 27, 2003
multicast
received without error are counted here.
OctetsReceivedOk: A total octet count for all
frames received without error.
FramesLostRxErrors: This is a count of
frames that would otherwise be received by
the IP100, but could not be accepted due to
an overrun condition in the RxFifo.
destination
address
that
are
8
PCI Bus Master Operation
The IP100 supports all of the PCI memory
commands and decides on a burst-by-burst basis
which command to use in order to maximize bus
efficiency. The list of PCI memory commands is
shown below. For all commands, “read” and “write”
are with respect to the IP100 (i.e. read implies the
IP100 obtains information from an off-chip location,
write implies the IP100 sends information to an
off-chip location).
Memory Read (MR)
Memory Read Multiple (MRM).
Memory Write (MW)
Memory Write Invalidate (MWI)
MR is used for all fetches of descriptor information.
For reads of transmit frame data, MR, or MRM is
used, depending upon the remaining number of
bytes in the fragment, the amount of free space in
the TxFIFO, and whether the RxDMA Logic is
requesting a bus master operation.
MW is used for all descriptor writes. Writes of
receive frame data use either MW or MWI,
depending upon the remaining number of bytes in
the fragment, the amount of frame data in the
RxFIFO, and whether the TxDMA Logic is
requesting a bus master operation.
The IP100 provides three configuration bits to
control the use of advanced memory commands.
The MWlEnable bit in the ConfigCommand
configuration register allows the host to enable or
disable the use of MWI. The MWIDisable bit in
DMACtrl allows the host system the ability to disable
the use of MWI. MWIDisable is cleared by default,
enabling MWI.
The IP100 provides a set of registers that control the
PCI burst behavior. These registers allow a trade-off
to be made between PCI bus efficiency and under
run/overrun frequency. Arbitration logic within the
PCI Bus Interface block accepts bus requests from
the TxDMA Logic and RxDMA Logic. The TxDMA
Logic uses the TxDMABurstThresh register, as
described in the TxDMA Logic section, to delay the
bus request until there is enough free space in the
TxFIFO for a long, efficient burst. The TxDMA Logic
can also make an urgent bus request as described
in the TxDMA Logic section, where burst efficiency
is sacrificed in favor of avoiding a TxFIFO under run
condition.
The RxDMA process is described in the RxDMA
Logic section. Typically, RxDMA requests will be
forwarded to the Arbiter, however RxDMA Urgent
Requests are also possible in order to prevent
RxFIFO overruns.
9
Power Management
The IP100 supports operating system directed
power management according to the ACPI
specification. Power management registers in the
PCI configuration space, as defined by the PCI Bus
Power
Management
Revision 1.0 are described in 10.0.
The IP100 supports several power management
states. The PowerState field in the PowerMgmtCtrl
register determines IP100’s current power state.
The power states are defined as follows:
D0 Uninitialized (power state 0) is entered as
a result of hardware reset, or after a transition
from D3 Hot to D0. This state is the same as
D0 Active except that the PCI configuration
registers are uninitialized. In this state, the
IP100 is unable to respond to PCI I/O,
memory and configuration cycles and can not
operate as a PCI master The IP100 cannot
signal wake (PMEN) from the D0 state.
D0 Active (power state 0) is the normal
operational power state for the IP100. In this
state, the PCI configuration registers have
been initialized by the system, including the
IoSpace, MemorySpace, and Bus-Master bits
in ConfigCommand, so the IP100 is able to
respond to PCI I/O, memory and configuration
cycles and can operate as a PCI master. The
IP100 cannot signal wake (PMEN) from the
D0 state.
D1 (power state 1) is a “l(fā)ight-sleep” state. The
Interface
specification,
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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