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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 40/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
10.4.3 DebugCtrl
Class............................. LAN I/O Registers, Interrupt
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x1c
Default .......................... 0x00
Width ............................ 8 bits
The DebugCtrl register configures the IP100 to enable or disable logic to handle known failure modes.
BIT
BIT NAME
R/W
0
RetryLockEnable
R/W
Retry Lock Enable. RetryLockEnable configures the IP100 DMA
operation if a retry deadlock condition is encountered. A retry
deadlock may occur if a PCI transaction between the IP100 and the
host system is terminated with a Retry PCI command. In this
situation, the IP100 DMA arbitration logic may switch between the
up and down operations which may result in a second PCI
transaction request onto the PCI bus. This second PCI transaction
request must complete before the original, retried transaction is
placed back onto the PCI bus.
The scenario described above situation is a violation of PCI protocol
and may create a deadlock situation if IP100 is interacting with a
PCI master device (i.e. system controller or bridge) which requires
transactions to complete in order.
If RetryLockEnable is a logic 0, the IP100 will operate as described
above, and may deadlock if a PCI transaction is terminated with a
retry.
If RetryLockEnable is a logic 1, and a transaction is terminated with a
retry, the IP100 will remain operating in its current state (up or down).
7..1
Reserved
N/A
Reserved for future use.
10.4.4 DMACtrl
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x00
Default .......................... 0x00000000
Width ............................ 32 bits
DMACtrl controls some of the bus master functions in the receive DMA and transmit DMA logic, and contains
status bits. DMACtrl is cleared by a reset.
BIT
BIT NAME
R/W
0
RxDMAHalted
R
Receive DMA Halted. RxDMAHalted is a logic 1 whenever receive
DMA is halted by setting RxDMAHalt or an implicit halt due to fetching
a RFD with RxDMAComplete in RxFrameStatus already a logic 1.
RxDMAHalted is cleared by setting RxDMAResume to a logic 1.
1
TxDMACmplReq
R
Transmit DMA Complete Request. TxDMACmplReq is equivalent to
the TxDMAIndicate field in the TxFrameControl of the current TFD.
2
TxDMAHalted
R
Transmit DMA Halted. TxDMAHalted is a logic 1whenever transmit
DMA is halted by setting TxDMAHalt. TxDMAHalted is cleared by
setting TxDMAResume to a logic 1.
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
40/92
IP100-DS-R03
May 27, 2003
BIT DESCRIPTION
BIT DESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù) |
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| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
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| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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