參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁數(shù)： 71/92頁
文件大小： 2801K
代理商： IP100
IP100
10.6.1 CacheLineSize
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x0c
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
7..0
CacheLineSize
R/W
IP100-DS-R03
May 27, 2003
71/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT DESCRIPTION
Cache Line Size. The system BIOS writes the system’s cache line
size into CacheLineSize. The host system uses CacheLineSize to
optimize PCI bus master operation (choosing the best memory
command, etc.). The value in CacheLineSize represents the number
of double words in a cache. CacheLineSize values must be a power
of two, from 0x04 to 0x80 (giving a range of 16 to 512 bytes).
CacheLineSize values which are not a power of two, between 4 and
128 are interpreted as 0x00.
10.6.2 CapId
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x50
Default .......................... 0x01
Width ............................ 8 bits
BIT
BIT NAME
R/W
7..0
CapId
R
BIT DESCRIPTION
Capabilities ID. CapId indicates the type of the capability data
structure for the IP100. CapId is set to the value 0x01 to indicate a
PCI Power Management structure.
10.6.3 CapPtr
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x34
Default .......................... 0x50
Width ............................ 8 bits
BIT
BIT NAME
R/W
7..0
CapPtr
R
BIT DESCRIPTION
Capabilities Pointer. CapPtr indicates the beginning of a chain of
registers which describe enhanced functions. CapPtr register
returns 0x50, which is the address of the first in a series of power
management registers.
10.6.4 CISPointer
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset.............. 0x28
Default Value ................ 0x00000802
Width ............................ 32 bits
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