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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 39/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
BIT
22
IP100-DS-R03
May 27, 2003
39/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT NAME
Host
R/W
W
BIT DESCRIPTION
Host Reset. Host selects (when a logic 1) or excludes (when a logic
0) the IP100 host bus interface logic functions and registers for/from
reset based on the value of the GlobalReset bit. The Host bit is
self-clearing.
Automatic Initialization Reset. AutoInit selects (when a logic 1) or
excludes (when a logic 0) the IP100 auto-initialization logic function
for/from re-loading IP100 parameters from an EEPROM based on
the value of the GlobalReset bit. The AutoInit bit is self-clearing.
Reserved for future use.
Interrupt Request. When InterruptRequest is a logic 1, the
IntRequested bit of the IntStatus register is set to a logic 1.
InterruptRequest is self-clearing.
Reset Busy. When ResetBusy is a logic 1 a reset process is in
progress. After asserting a reset using the GlobalReset, RxReset, or
TxReset bits, the ResetBusy bit must be polled (or periodically read)
until it is a logic 0 indicating the reset operation is complete.
Reserved for future use.
Reserved for future use.
Card Bus Select. If Reserved/CardBus is a logic 1, the host interface of
the IP100 is CardBus. If Reserved/CardBus is a logic 0, the host
interface of the IP100 is PCI (including miniPCI). Reserved/CardBus is
set via EA[0] (with a logic inversion) at the end of a reset via the RSTN
signal or a IP100 power cycle. When Reserved/CardBus is a logic 0,
the CardBus functionality needs to be disabled.
Reserved for future use.
23
AutoInit
W
24
25
Reserved
InterruptRequest
N/A
W
26
ResetBusy
R/W
29..27
30
Reserved
Reserved/CardBus
N/A
N/A
R
31
Reserved
N/A
10.4.2 Countdown
Class............................. LAN I/O Registers, Interrupt
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x18
Default .......................... 0x00000000
Width ............................ 16 bits
Countdown is a programmable down-counter that will generate an interrupt upon its expiration. If the
CountdownIntEnable bit in DMACtrl is set, the IntRequested interrupt will be generated when Countdown counts
through zero. Countdown has two modes of operation that is selected by the CountdownMode bit in DMACtrl.
When CountdownMode is cleared, Countdown is loaded by the host software with an initial countdown value,
then decrements at a rate determined by the CountdownSpeed bit in DMACtrl. When Countdown reaches zero, it
continues to count down, wrapping to 0xFFFF. When CountdownMode is set, Countdown begins counting only
when TxDMAComplete in IntStatus becomes set.
BIT
BIT NAME
R/W
15..0
Countdown
R
Value of current state of Countdown timer.
BIT DESCRIPTION
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| IP1060AN | Analog IC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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