參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁(yè)數(shù)： 59/92頁(yè)
文件大?。?/td> 2801K
代理商： IP100
IP100
BIT
6..0
IP100-DS-R03
May 27, 2003
59/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT NAME
TxDMAPollPeriod
R/W
R/W
BIT DESCRIPTION
Transmit DMA Poll Period. The number of 320ns intervals between
polls of the current TFD’s TxDMANextPtr field.
Reserved for future use.
7
Reserved
N/A
10.4.32 TxDMAUrgentThresh
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x09
Default .......................... 0x04
Width ............................ 8 bits
When the number of used bytes in the transmit FIFO falls below the value in the TxDMAUrgentThresh, the
transmit DMA logic will make an urgent bus master request. An urgent transmit DMA request will have priority
over the receive DMA, unless it is also making an urgent request. A transmit DMA urgent request is not subject to
the TxDMABurstThresh constraint. The relaxation of the TxDMABurstThresh constraint for this condition is
because the transmit FIFO is close to under run, and burst efficiency is sacrificed to avoid FIFO under run.
TxDMAUrgentThresh represents data in the transmit FIFO in multiples of 32 bytes.
BIT
BIT NAME
R/W
5..0
TxDMAUrgent-
Thresh
words which must be occupied in the transmit FIFO to avoid
assertion of a transmit DMA Urgent Request.
7..6
Reserved
N/A
Reserved for future use.
10.4.33 TxReleaseThresh
Class............................. LAN I/O Registers, FIFO Control
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x5d
Default .......................... 0x08
Width ............................ 8 bits
TxReleaseThresh determines how much data of a frame must be transmitted before the transmit FIFO space can
be released for use by another frame. Once the number of bytes equal to the value in TxReleaseThresh have
been transmitted, that number of bytes are discarded from the transmit FIFO. Thereafter, bytes are discarded as
they are transmitted to the network. A value of 0xff in TxReleaseThresh disables the release mechanism and
transmit FIFO frame space is not released until the entire frame is transmitted. The TxReleaseError bit in the
TxStatus register indicates when a frame experiences a collision after its release threshold has been crossed,
preventing MAC from retry. When a release error occurs, the transmitter is disabled, and the frame’s ID or
sequence number is visible in TxStatus.
BIT
BIT NAME
R/W
7..0
TxReleaseThresh
R/W
Transmit Release Threshold. The number of 16 byte words which
must be transmitted before the space in the transmit FIFO occupied
by the transmitted data can be released. To avoid excessive release
errors due to in-window collisions, TxReleaseThresh should be
greater than or equal to 0x04.
BIT DESCRIPTION
R/W
Transmit DMA Urgent Threshold. The minimum number of 32-byte
BIT DESCRIPTION
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