參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁數(shù)： 52/92頁
文件大?。?/td> 2801K
代理商： IP100
IP100
Note: External loopback is controlled by the PHY. To utilize external loopback, the host system must enable a
loopback mode within the PHY using the MII Management Interface. For the true “on-the-wire” loopback mode,
use a loopback plug (connector), clear the FIFOLoopback, and MACLoopback and any PHY loopback bits to zero,
set the FullDuplexEnable bit to a logic 1, and enable the full duplex mode within the PHY.
10.4.19 MACCtrl1
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x52
Default .......................... 0x0000
Width ............................ 16 bits
BIT
BIT NAME
R/W
0
CollisionDetect
R
Collision Detect. CollisionDetect provides a real-time indication of
the state of the COL signal within the IP100.
1
CarrierSense
R
Carrier Sense. CarrierSense provides a real-time indication of the
state of the CRS signal within IP100.
2
TxInProg
R
Transmit In Progress. TxInProg provides a real-time indication that a
frame is being transmitted. If TxInProg is a logic 1, a frame
transmission is in progress. TxInProg is used by the host system
during under run recovery to delay before setting the issuing a
TxReset bit in the AsicCtrl register.
3
TxError
R
Transmit Error. If a transmit under run occurs (indicated via the
TxUnderrun bit of the TxStatus register), TxError is a logic 1,
indicating that the transmitter needs to be reset via the TxReset bit
in the AsicCtrl register.
4
Reserved
N/A
Reserved for future use.
5
StatisticsEnable
W
Statistics Enable. Writing a logic 1 to StatisticsEnable will enable the
IP100’s statistic registers. The state (enabled/disabled) of the
IP100’s statistic registers is shown via StatisticsEnabled.
6
StatisticsDisable
W
Statistics Disable. Writing a logic 1 to StatisticsDisable will disable
the IP100’s statistic registers. The state (enabled/disabled) of the
IP100’s statistic registers is shown via StatisticsEnabled.
7
StatisticsEnabled
R
Statistics Enabled. If StatisticsEnabled is a logic 1, the IP100’s
statistic registers are enabled.
8
TxEnable
W
Transmit Enable. Writing a logic 1 to TxEnable will enable the IP100
to transmit frames. The state (enabled/disabled) of the IP100’s
transmitter is shown via TxEnabled.
9
TxDisable
W
Transmit Disable. Writing a logic 1 to TxDisable will disable the
IP100 from transmitting frames. The state (enabled/disabled) of the
IP100’s transmitter is shown via TxEnabled.
10
TxEnabled
R
Transmit Enabled. If TxEnabled is a logic 1, the IP100’s transmitter
is enabled.
11
RxEnable
W
Receive Enable. Writing a logic 1 to RxEnable will enable the IP100
to receive frames. The state (enabled/disabled) of the IP100’s
receiver is shown via RxEnabled.
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
52/92
IP100-DS-R03
May 27, 2003
BIT DESCRIPTION
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