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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 60/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
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IP100
10.4.34 TxStatus
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x46
Default .......................... 0x0000
Width ............................ 16 bits
TxStatus returns the status of frame transmission or transmission attempts. TxStatus actually implements a
queue of up to 31 transmit status bytes. A write of an arbitrary value to TxStatus will advance the queue to the
next transmit status byte.
BIT
BIT NAME
R/W
0
Reserved
N/A
Reserved for future use.
1
TxReleaseError
R
Transmit Release Error. If TxReleaseError is a logic 1, a transmit release
error occurred, meaning that the frame transmission experienced a
collision after the front of the frame had already been released to the
transmit FIFO free space. See TxReleaseThresh register.
2
TxStatusOverflow
R
Transmit Status Overflow. If TxReleaseError is a logic 1, the TxStatus
stack is full and as a result the transmitter has been disabled. Writing
an arbitrary value to TxStatus clears TxReleaseError but the
transmitter must be re-enabled via the TxEnable bit of the MACCtrl1
register before transmissions may resume.
3
MaxCollisions
R
Maximum Collisions. If MaxCollisions is a logic 1, a frame was not
successfully transmitted due to encountering 16 collisions. The
TxEnable bit of the MACCtrl1 register is used to recover from this
condition. The frame is discarded from the transmit FIFO.
4
TxUnderrun
R
Transmit Underrun. If TxUnderrun is a logic 1 the frame experienced
an under run during the transmit process because the host system
was unable to supply the frame data fast enough to keep up with the
network data rate. An under run will halt the transmitter and the
transmit FIFO. The TxReset bit of the AsicCtrl register is used to
recover from an under run condition.
5
Reserved
N/A
Reserved for future use.
6
TxIndicateReqd
R
Transmit Indicate Requested. If TxIndicateReqd is a logic 1, the
TxIndicate bit of the TxFrameControl field for the corresponding TFD
was set.
7
TxComplete
R
Transmit Complete. If TxComplete is a logic 0, then the
TxReleaseError, TxStatusOverflow, MaxCollisions, TxUnderrun,
and TxIndicateReqd bits are undefined. If the host chooses to poll
TxStatus while waiting for a frame transmission to complete, then
TxComplete is used to determine that a frame transmission attempt
has either experienced an error, or has completed successfully with
the TxIndicate bit set in the TxFrameControl field of the
corresponding TFD.
15..8
TxFrameId
R/W
Transmit Frame Identification. TxFrameId contains the value from
the FrameId subfield within the TxFrameControl field of TFD
corresponding to the currently transmitting or most recently
transmitted frame. Host systems can use TxFrameId during transmit
error recovery by scanning through the TFD’s in the transmit DMA
list, searching for a match between the TxFrameId value and a
TxFrameControl’s, FrameId value in the TFD.
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
60/92
IP100-DS-R03
May 27, 2003
BIT DESCRIPTION
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相關代理商/技術參數(shù) |
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