- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360868 > IP100 PCI 10/100M Single Chip Ethernet Controller PDF資料下載
參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 80/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁當前第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
IP100
10.6.21 PowerMgmtCtrl
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x54
Default Value ................ 0x4000
Width ............................ 16 bits
PowerMgmtCtrl allows control over the power state and the power management interrupts.
BIT
BIT NAME
R/W
1..0
PowerState
R/W
Power State. PowerState indicates the current power state of the
IP100. If PowerState is set to a value other than 0x0, the IP100 will
not respond to PCI I/O or memory cycles, nor will the IP100 be able
to generate PCI bus master cycles.
BIT 1
BIT 0
0
0
0
1
1
0
1
1
7..2
Reserved
N/A
Reserved for future use.
8
PmeEn
R/W
Power Management Event Enable. When PmeEn is a logic 1, the
IP100 is allowed to report wake events on the WAKE signal. The
criteria for generating wake events is defined by the WakeEvent
register. PmeEn is loaded from the ConfigParm field of an EEPROM
during auto initialization of the IP100.
12..9
DataSelect
R/W
Data Select. DataSelect is used to select which data is to be
reported through the Data register and DataScale field.
14..13
DataScale
R
Data Scale. DataScale indicates the scaling factor to be used when
interpreting the value of the Data register. The interpretation of the
scale values is defined as follows:
DATASCALE
0x0
0x1
0x2
0x3
15
PmeStatus
R/W
Power Management Event Status. When PmeStatus is a logic 1 a
wake event has occurred. PmeStatus may be a logic 1 regardless of
the value of PmeEn. Writing a logic 1 to PmeStatus will set
PmeStatus to a logic 0. Writing a logic 0 to PmeStatus has no effect.
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
80/92
IP100-DS-R03
May 27, 2003
BIT DESCRIPTION
POWER STATE
D0
D1
D2
D3
SCALE FACTOR
Unknown
0.1
0.01
0.001
相關PDF資料 |
PDF描述 |
|---|---|
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
發(fā)布緊急采購，3分鐘左右您將得到回復。