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IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
24/92
IP100-DS-R03
May 27, 2003
BIT
9
BIT NAME
100BASE-T4
R/W
R
BIT DESCRIPTION
1 = 100BASE-T4 capable.
0 = 100BASE-T4 incapable.
1 = 100BASE-TX Full Duplex capable.
0 = Not 100BASE-TX Full Duplex capable.
1 = 100BASE-TX Half Duplex capable.
0 = Not 100BASE-TX Half Duplex capable.
1 = 10BASE-T Full Duplex capable.
0 = Not 10BASE-T Full Duplex capable.
1 = 10BASE-T Half Duplex capable.
0 = Not 10BASE-T Half Duplex capable.
Selector Field
8
100BASE-TX Full
Duplex
100BASE-TX Half
Duplex
10BASE-T Full
Duplex
10BASE-T Half
Duplex
Selector Field
R
7
R
6
R
5
R
4..0
R
10.1.7 Auto-Negotiation Expansion
Class............................. PHY Registers
Access Method............. Accessed through PhyCtrl register
Register Address.......... 0x06
Default .......................... 0x0000
Width ............................ 16 bits
BIT
BIT NAME
15..5
Reserved
4
Parallel Detection
R/W
N/A
R
BIT DESCRIPTION
Reserved for future use.
1= Parallel detection fault.
0 = No parallel detection fault.
If Parallel Detection is a logic 1, Parallel Detection will remain a logic
1 until the parallel detection fault condition no longer exists, and
Parallel Detection has been read by the host system.
1 = Link partner Next Page capable.
0 = Link partner not Next Page capable.
1 = Local device Next Page capable.
0 = Local device not Next Page capable.
1 = New page received.
0 = New page not received.
If Page Received is a logic 1, Page Received will remain a logic 1
Page Received has been read by the host system.
1 = Link partner Auto-Negotiation capable.
0 = Link partner not Auto-Negotiation capable.
3
Link partner Next
Page Able
Next Page Able
R
2
R
1
Page Received
R
0
Link partner
Auto-Negotiation
Able
R