- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360868 > IP100 PCI 10/100M Single Chip Ethernet Controller PDF資料下載
參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 68/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁當前第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
IP100
10.5.13 MultipleCollisionFrames
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x76
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
7..0
MultipleCollision-
Frames
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
68/92
IP100-DS-R03
May 27, 2003
R/W
R/W
BIT DESCRIPTION
Multiple Collision Frames is a count of the number of frames that are
involved in more than one collision and are subsequently
transmitted successfully. MultipleCollisionFrames will wrap around
to zero after reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.4.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when MultipleCollisionFrames reaches a value of
0xC0. MultipleCollisionFrames is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of MultipleCollisionFrames also clears the register.
10.5.14 OctetsReceivedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x68
Default .......................... 0x00000000
Width ............................ 32 bits (accessible as 2, 16 bit words)
BIT
BIT NAME
19..0
OctetsReceivedOk
R/W
R/W
BIT DESCRIPTION
Octets Received OK is the count of the number of data and padding
octets in frames that are successfully received. OctetsReceivedOk
does not include frames received with frames too long, FCS, length
or alignment errors, or frames lost due to internal MAC sublayer
error (i.e. overrun). OctetsReceivedOk will wrap around to zero after
reaching 0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.14.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when OctetsReceivedOk reaches a value of
0xC0. OctetsReceivedOk is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of OctetsReceivedOk also clears the register.
Reserved for future use.
31..20
Reserved
N/A
相關PDF資料 |
PDF描述 |
|---|---|
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
發(fā)布緊急采購，3分鐘左右您將得到回復。