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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 54/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
54/92
IP100-DS-R03
May 27, 2003
BIT
3
4
BIT NAME
Reserved
PhyDuplexPolarity
R/W
N/A
R/W
BIT DESCRIPTION
Reserved for future use.
PHY Duplex Polarity. If PhyDuplexPolarity is a logic 0, the duplex
status signal between the PHY and the MAC is active low.
PHY Duplex Status. If PhyDuplexStatus is a logic 1, the PHY is
operating in full duplex mode. If PhyDuplexStatus is a logic 0, the
PHY is operating in half duplex mode.
PHY Speed Status. PhySpeedStatus provides a real-time indication
of the IP100’s PHY speed. If PhySpeedStatus is a logic 1, the
IP100’s PHY is operating at 100Mbps operation. If PhySpeedStatus
is a logic 0, the IP100’s PHY is operating at 10Mbps operation.
PHY Link Status. PhyLinkStatus provides a real-time indication of
the IP100’s PHY link state. If PhyLinkStatus is a logic 1, the IP100’s
PHY link is up. If PhyLinkStatus is a logic 0, the IP100’s PHY link is
down.
5
PhyDuplexStatus
R
6
PhySpeedStatus
R
7
PhyLinkStatus
R
10.4.22 ReceiveMode
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x5c
Default .......................... 0x00
Width ............................ 8 bits
ReceiveMode sets the receive filter of the IP100.
BIT
BIT NAME
0
ReceiveUnicast
R/W
R/W
BIT DESCRIPTION
Receive Unicast. If ReceiveUnicast is a logic 1, the IP100 receives
unicast frames (frames where the DA field matches the 48-bit value
in the StationAddress register.
Receive Multicast. If ReceiveMulticast is a logic 1, the IP100
receives all multicast frames, including broadcast frames.
Receive Broadcast. If ReceiveBroadcast is a logic 1, the IP100
receives all broadcast frames.
Receive All Frames. If ReceiveAllFrames is a logic 1, the IP100
receives all frames.
Receive Multicast Hash. If ReceiveMulticastHash is a logic 1, the
IP100 receives all which pass the hash filtering mechanism defined
in the HashTable register..
Receive IP Multicast. If ReceiveIPMulticast is a logic 1, the IP100
receives all multicast IP datagrams, which are mapped into Ethernet
multicast frames with destination address of 01:00:5e:xx:xx:xx as
defined in RFC 1112 and RFC 1700. The first 3 bytes require exact
match, and the last 3 bytes are ignored.
Reserved for future use.
1
ReceiveMulticast
R/W
2
ReceiveBroadcast
R/W
3
ReceiveAllFrames
R/W
4
ReceiveMulticast-
Hash
R/W
5
ReceiveIPMulticast
R/W
7..6
Reserved
N/A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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