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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 19/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
LinkEventEnable is cleared, LinkEvent is set in
WakeEvent, and (if it is enabled) the PMEN signal is
asserted.
9.1
Wake Event
IP100-DS-R03
May 27, 2003
19/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
When a desired wake event occurs, the IP100 sets
the appropriate event bit in the WakeEvent register,
sets the PmeStatus bit in the PowerMgmtCtrl
register, and asserts the WAKE signal.
The host system responds to PMEN by scanning
the power management configuration registers of all
devices, looking for the device which asserted
PMEN. If the device with the IP100 signaled wake,
the system will find PmeStatus set in IP100’s
PowerMgmtCtrl register. The operating system then
clears the PmeEn bit in the PowerMgmtCtrl register
causing PMEN to be de-asserted.
The operating system raises the power state
(probably to D0) by writing to the PowerState bits in
the PowerMgmtCtrl register. If the IP100 was
previously in the D3 state, PCI configuration is lost
and must be restored by the operating system.
The host system must set TxReset to clear any
wake patterns out of the transmit FIFO (if this is not
done, the patterns will be treated as frames and
transmitted once the transmitter is enabled).
The host system reads the WakeEvent register to
determine the wake event, and if requested, passes
it back to the operating system. The host system
restores any volatile state that was saved in the
power down sequence. The host system re-enables
interrupts by programming IntEnable. The host
system restores the RxDMAList (and any other data
structures required for operation). Any wake
packets in the receive FIFO are transferred by
receive DMA and passed to the operating system.
9.2
Power Down
D0u and D0i are mutually exclusive. The moment
that
the
IoBaseAddress
MemBaseAddress is written by the host, then IP100
enters D0u. When D0u is active, the PHY is
completely powered down and all clocks (AsicClk,
TxClk, RxClk) are gated off except PciClk. The
IP100 consumes less than 70 mA in D0u. Make
sure that the LED drivers are off. When IP100 is in
D0i, the PHY is powered up and ready to transmit
and receive packets. In Forced Config mode
(motherboard applications), IP100 is always in D0i
mode. Another way to indicate D0u is to check the
non-zero value in the programmable field of
IoBaseAddress or MemBaseAddress. In WOL the
PHY should be fully functional to receive Magic
Packets. In WOL mode, D0u should be forced to low
before passing to the PHY.
When in the D3 state, if PMEN is de-asserted on the
PCI bus the IP100 will enter Power Down. When in
Power Down mode, the PHY is completely powered
down. All clocks (AsicClk, TxClk, RxClk) except
PciClk are gated off. When the PCI bus is powered
down, the IP100 consumes less than 5 mA.
register
or
the
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相關(guān)代理商/技術(shù)參數(shù) |
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| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
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| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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