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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 32/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
32/92
IP100-DS-R03
May 27, 2003
10.3 Wake Event Data Structures
The first Wake Event Data Structure is the Pseudo Packet. A Pseudo Packet is a set of patterns loaded into the
IP100 TxFIFO which specify bytes to be examined within received frames. A CRC is calculated over these bytes
and compared with a CRC value supplied in the Pseudo Packet. If a match is found, the IP100 issues a Wake Event.
The matching technique may result in false wake events being reported to the host system. Each Pseudo Packet
consists of one or more byte-offset/byte-count pairs (or Pseudo Patterns), a terminator symbol, and a 4-byte CRC
value. The byte offsets within the Pseudo Patterns indicate the number of received frame bytes to be skipped in
order to reach the next group of bytes to be included in the CRC calculation. The byte-counts within the Pseudo
Patterns indicate the number of bytes in the next group to be included in the CRC calculation. The terminator
indicates the end of the Pseudo Patterns for the Pseudo Packet. Immediately following the terminator is a 4-byte
CRC. If there is another Pseudo Packet, it will immediately follow the CRC value.
The second Wake Event Data Structure is the Magic Packet. Magic Packets are uniquely formatted frames, which
upon reception invoke a Wake Event by the IP100. Once the IP100 has been placed in Magic Packet mode and
put to sleep, it scans all incoming frames addressed to it for a data sequence consisting of a synchronization
stream followed immediately by 16 consecutive repetitions of the station’s own 48-bit Ethernet MAC station
address. The sequence can be located anywhere within the received frame.
The pseudo packet and Magic Packet data structures are shown in Figure 12
IP100
pseudo
packet
PseudoPattern 1
Terminator
PseudoPattern n
PseudoCRC
0x00
0x01
0x00+n+1
0x00+n
0x00+n-1
Received Packet
0x00
0x06
Ethernet Header
MagicSyncStream
MagicSequence
Ethernet CRC
Magic
Packet
TM
FIGURE 12 : Wake Event Data Structures, Pseudo Packet and Magic Packet
相關(guān)PDF資料 |
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| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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