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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 8/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
Integrated 10/100 Ethernet MAC + PHY
3
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
8/92
IP100-DS-R03
May 27, 2003
Acronyms and Glossary
LAN
MAC
Local Area Network
Media Access Control Layer, or a
device implementing the functions of
this layer (a Media Access Controller)
Peripheral Component Interface
Network Interface Cards
First In First Out
Erasable Programmable Read Only
Memory
EEPROM Electrically Erasable Programmable
Read Only Memory
LED
Light Emitting Diode
PHY
Physical Layer, or device implementing
functions of the Physical Layer
CSMA/CD Carrier Sense Multiple Access with
Collision Detect
FCS
Frame Check Sequence
SFD
Start of Frame Delimiter
CRC
Cyclic Redundancy Check
IP
Internet Protocol
TFD
Transmit Frame Descriptor
RFD
Receive Frame Descriptor
DMA
Direct Memory Access
ACPI
Advanced Configuration and Power
Management
4
Standards Compliance
PCI
NIC
FIFO
EPROM
The IP100 implements functionality compliant with
the following standards:
IEEE 802.3 Fast Ethernet
IEEE 802.3 Full Duplex Flow Control
PCI Local Bus Revision 2.2
PCI Bus Power Management Interface
Revision 1.1
ACPI Revision 1.0
5
Functional Description
The IP100 is composed of various functional blocks
as shown in Figure 1 on page 2. An overview of the
functions performed by each block are as follows:
5.1
Media Access Control
The MAC block implements the IEEE Ethernet
802.3 Media Access Control functions with 802.3
Full Duplex and Flow Control enhancements. In half
duplex mode, the MAC implements the CSMA/CD
algorithm. Full duplex mode by definition does not
utilize CSMA/CD, allowing data to be transmitted on
demand. An optional flow control mechanism in full
duplex mode is provided via the MAC Control
PAUSE function. Additionally, the MAC also
performs the following functions in either half or full
duplex mode:
Optional transmit FCS generation
Padding to the minimum legal frame size
Preamble and SFD generation
Preamble and SFD removal
Receive frame FCS checking and optional
FCS stripping
Receive frame destination address matching
Support for multicast and broadcast frame
reception or rejection (via filtering)
Selective InterFrame Gap to avoid capture
effect
MAC Loopback
The MAC is responsible for generation of hardware
signals to update the internal statistics counters.
5.2
Physical Layer
The IP100 supports both IEEE 802.3 100BASE-TX
and 100BASE-FX signaling. The 100BASE-X
transmit logic performs 4B5B encoding/decoding,
parallel to serial, and serial to parallel conversion,
and
NRZ-NRZI
signaling.
100BASE-TX, scrambling and MLT-3 encoding are
also done before the data is transmitted on to the
media. The receive 100BASE-X circuitry, recovering
data from either an MLT-3 signal (100BASE-TX) or
a PECL input (100BASE-FX), generates four bit
nibbles to send to the MAC.
The Media Dependent Interface selection is done by
the FSD pin. If the FSD pin is connected directly to
GND, the IP100 PHY layer is operating in
100BASE-TX mode. If FSD is connected to the
output of an optical module, then the PHY layer is in
100BASE-FX mode.
The IP100 PHY also includes a full set of registers
for controlling the PHY as outlined in the IEEE 802.3
specification.
5.3
On-Chip Voltage Regulator
In
the
case
of
The IP100 has an integrated voltage regulator for
reduced system cost. The voltage regulator is used
to provide the 2.5 V power to the PCB. When used
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相關(guān)代理商/技術(shù)參數(shù) |
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| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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