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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 51/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
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IP100
BIT
5
IP100-DS-R03
May 27, 2003
51/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT NAME
FullDuplexEnable
R/W
R/W
BIT DESCRIPTION
Full Duplex Enable. Setting FullDuplexEnable to a logic 1 configures
the IP100 to function in a full duplex manner. When operating in full
duplex, the IP100 disables transmitter deference to receive traffic,
allowing simultaneous receive and transmit traffic. Operation in full
duplex has the side-effect of disabling CarrierSenseErrors statistics
collection, since full duplex operation requires carrier sense to be
masked to the transmitter. TxReset and RxReset bits in AsicCtrl must
be set for changes ofFullDuplexEnable to take effect.
Receive Large Frames. RcvLargeFrames determines the frame size
at which the RxOversizedFrame bit of the RxFrameStatus field is set
for receive frames. When RcvLargeFrames is a logic 0, minimum
OversizedFrame size is 1514 bytes. When RcvLargeFrames is set,
minimum OversizedFrame size is 4491 bytes. (This value was the
maximum FDDI frame size of 4500 bytes, subtracting bytes for fields
that have no Ethernet equivalent.)
The frame size at which an OversizedFrame error will be flagged
includes the destination and source addresses, the type/length field,
and the FCS field.
Reserved for future use.
Flow Control Enable. If FlowControlEnable is a logic 0, the IP100
treats all incoming frames as data frames. If FlowControlEnable is a
logic 1, flow control is enabled and the IP100 will act upon incoming
flow control PAUSE frames. If FlowControlEnable is a logic 1,
FullDuplexEnable should also be set to a logic 1.
Receive FCS. If RcvFCS is a logic 1, the IP100 will include the
receive frame’s FCS along with the frame data transferred to the host
system. If RcvFCS is a logic 0, the IP100 will remove the FCS from
the frame before transferring the frame to the host system. The state
of RcvFCS does not affect the IP100’s checking of the frame’s FCS
and its posting of FCS errors. RcvFCS should only be changed when
the receiver is disabled (via the RxDisable bit of the MACCtrl1
register) and after resetting the receive FIFO (via the FIFO bit of the
AsicCtrl register).
FIFO Loopback. If FIFOLoopback is a logic 1, the IP100 will enter
FIFO Loopback Mode and force data to loopback from the transmit
FIFO directly into the receive FIFO. When using FIFO Loopback
Mode, it is the host system’s responsibility to ensure that proper
interframe spacing is ensured. To accommodate proper interframe
spacing, the host system must not load more than one transmit frame
into the transmit FIFO at a time while in FIFO Loopback Mode. The
TxReset and RxReset bits of the AsicCtrl register must be set after
changing the value of FIFOLoopback.
MAC Loopback. If MACLoopback is a logic 1, the IP100 will enter
MAC Loopback Mode and force data to loopback from the MAC
transmit interface to the MAC receive interface. The TxReset and
RxReset bits in AsicCtrl register must be set after changing the value
of MACLoopback.
Reserved for future use.
6
RcvLargeFrames
R/W
7
8
Reserved
FlowControlEnable
N/A
R/W
9
RcvFCS
R/W
10
FIFOLoopback
R/W
11
MACLoopback
R/W
15..12
Reserved
N/A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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