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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 15/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
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IP100
number of bytes transferred by RxDMA for the
current RFD pointed to by the RxDMAListPtr
register. The host system can then perform memory
copies out of the RFD buffer concurrently with the
RxDMA operation.
6.5
Interrupts
IP100-DS-R03
May 27, 2003
15/92
Copyright
2003, IC Plus Corp.
All rights reserved.
The term “interrupt” is used loosely to refer to
interrupts and indications. An interrupt is the actual
assertion of the hardware interrupt signal on the PCI
bus. An indication, or a set bit in the IntStatus
register, is the reporting of any event enabled by the
host. The host system will configure the IP100 to
generate an interrupt for any indication that is of
interest to it. There are 11 different types of interrupt
indications that can be generated by the IP100. The
IntEnable register controls which of the 11 indication
bits can assert a hardware interrupt. In order for an
indication bit to be allowed to generate an interrupt,
its corresponding bit-position in IntEnable must be
set. When responding to an interrupt, the host reads
the IntStatus register to determine the cause of the
interrupt. The least significant bit of IntStatus,
InterruptStatus, is always set whenever any of the
interrupts are asserted. InterruptStatus must be
explicitly acknowledged (cleared) by writing a 1 into
the bit in order to prevent spurious interrupts on the
host bus.
Interrupts are acknowledged by the host carrying
out various actions specific to each interrupt.
7
Statistics
The IP100 implements 16 statistics counters of
various widths. Each statistic implemented complies
to the corresponding definition given in the IEEE
802.3 standard. Setting the StatisticsEnable bit in
the MACCtrl1 register enables the gathering of
statistics. Reading a statistics register will clear the
read register. Statistic registers may be read without
disabling statistics gathering. For diagnostics and
testing purposes, the host system may write a value
to a statistic register, in which case the value written
is added to the current value of the register.
Whenever one or more of the statistics registers
reaches 75% of its maximum value, an UpdateStats
interrupt is generated. Reading that statistics
register will acknowledge the UpdateStats interrupt.
A summary of the transmit and receive statistics
follows. Detailed descriptions of the statistic
registers related to data transmission and reception
can be found in the Registers and Data Structures
section.
7.1
Transmit Statistics
FramesTransmittedOk: The number frames of
all types transmitted without errors. Loss of
carrier is not considered to be an error by this
statistic.
BroadcastFramesTransmittedOk:
number of frames with broadcast destination
address that are transmitted without errors.
MulticastFramesTransmittedOk: The number
of frames with multicast destination address
that are transmitted without errors.
OctetsTransmittedOk: The number of total
octets for all frames transmitted without error.
FramesWithDeferredXmission: A count of
frames whose transmission was delayed on
it’s first attempt because network traffic.
FramesWithExcessiveDeferral:
transmission of a frame has been deferred for
an excessive period of time due to network
traffic, the event is recorded in this statistic.
SingleCollisionFrames:
transmitted without errors after one and only
one collision (including late collisions) are
counted by this register.
MultipleCollisionFrames:
transmitted without error after experiencing
from 2 through 15 collisions (including late
collisions) are counted here.
LateCollisions: Every occurrence of a late
collision (there could be more than one per
frame transmitted) is counted by this statistic.
FramesAbortedDueToXSColls:
transmission of a frame had to be aborted due
to excessive collisions, the event is recorded
in this statistic.
CarrierSenseErrors:
transmitted without error but experienced a
loss of carrier are counted by this statistic.
The
If
the
Frames
that
are
All
frames
If
the
Frames
that
were
7.2
Receive Statistics
FramesReceivedOk: Frames of all types that
are received without error are counted here.
BroadcastFramesReceivedOk:
broadcast destination address that are
received without error are counted here.
MulticastFramesReceivedOk:
Frames
of
Frames
of
Preliminary, Specification subject to change without notice.
相關PDF資料 |
PDF描述 |
|---|---|
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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