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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 45/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
10.4.9 FIFOCtrl
Class............................. LAN I/O Registers, FIFO Control
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x3a
Default .......................... 0x0000
Width ............................ 16 bits
FIFOCtrl provides various control and indications for the transmit FIFO and the receive FIFO diagnostic.
BIT
BIT NAME
R/W
0
RAMTest Mode
R/ W
RAM Tes t Mode. I f RAMTestMode is a logic 1, the FIFO RAM is in the
test mode.
8..1
Reserved
N/A
Reserved for future use.
9
RxOverrunFrame
R/ W
Receive Overrun Frame. RxOverrunFrame determines how the IP100
handles receive overrun frames. If RxOverrunFrame is a logic 0, the
IP100 discards all overrun frames. If RxOverrunFrame is a logic 1, the
IP100 will retain all overrun frames, so that they may be inspected by
the host for diagnostic purposes.
10
Reserved
N/A
Reserved for future use.
11
RxFIFOFull
R
Receive FIFO Full. If RxFIFOFull is a logic 1, the receive FIFO is full.
RxFIFOFull does not in itself indicate an overrun condition.
However, if more data is received while RxFIFOFull is a logic 1, an
overrun will occur. RxFIFOFull is cleared as soon as the receive
FIFO is no longer full.
13..12
Reserved
N/A
Reserved for future use.
14
Transmitting
R
Transmit Indicator. Transmitting is set to a logic 1 whenever a frame is
being transmitted or during a transmit deferral).
15
Receiving
R
Receive Indicator. Receiving is set to a logic 1 whenever a frame is
being received. No action is expected on the part of the host based on
the state of Receiving.
10.4.10 ForceEvent
Class............................. LAN I/O Registers, CardBus Status Change
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x2c
Default Value ................ 0x00000000
Width ............................ 32 bits
ForceEvent is used to force values in the FunctionEvent register. Writing a logic 1 to any bit in ForceEvent sets
the corresponding bit in the FunctionEvent register, simulating a status change event. If other functions are active,
they may alter the values previously forced into the FunctionEvent register.
BIT
BIT NAME
R/W
3..0
Reserved
N/A
Reserved for future use.
4
GWAKE
R/W
GWAKE. Writing a logic 1 to GWAKE sets the GWAKE bit of the
FunctionEvent
FunctionPresentState register.
14..5
Reserved
N/A
Reserved for future use.
15
INTR
R/W
INTR. Writing a logic 1 to INTR sets the INTR bit of the FunctionEvent
register, but not the INTR bit of the FunctionPresentState register.
IP100-DS-R03
May 27, 2003
45/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT DESCRIPTION
BIT DESCRIPTION
register,
but
not
the
GWAKE
bit
of
the
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