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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 36/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
10.4.1 AsicCtrl
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x30
Default .......................... 0x00004000 (default values for ExpRomSize, PhySpeed10, PhySpeed100, PhyMedia
are dependent on EEPROM settings, and ForcedConfig[1..0], ForcedCon-fig[2] are
dependent on ED signal pin states)
Width ............................ 32 bits
AsicCtrl provides chip-specific, non-host-related settings. The contents of the least significant byte of AsicCtrl are
read from EEPROM at reset.
BIT
BIT NAME
R/W
0
Reserved
N/A
Reserved for future use.
1
ExpRomSize
R
Expansion ROM Size. ExpRomSize specifies the size of the
Expansion ROM interfaced to the IP100. If the expansion ROM is
32kB, set ExpRomSize to a logic 0. If the expansion ROM is 64kB,
set ExpRomSize to a logic 1.
2
TxLargeEnable
R/W
Transmit Large Frames Enable. If TxLargeEnable is a logic 1, the
IP100 may transmit frames which are larger in size than the IP100
transmit FIFO.
3
RxLargeEnable
R/W
Receive Large Frames Enable. If RxLargeEnable is a logic 1, the
IP100 may receive frames which are larger than the IP100 receive
FIFO.
4
ExpRomDisable
R/W
Expansion ROM Disable. If ExpRomDisable is a logic 1, accesses to
the on-adapter Expansion ROM are disabled and read to the
Expansion ROM return 0x00000000 while writes to the Expansion
ROM are ignored.
5
PhySpeed10
R
Physical Device 10Mbps Capable. If PhySpeed10 is a logic 1, the
IP100 PHY is capable of operating at 10Mbps.
6
PhySpeed100
R
Physical Device 100Mbps Capable. If PhySpeed100 is a logic 1, the
IP100 PHY is capable of operating at 100Mbps.
7
PhyMedia
R
Physical Device Media Type. If PhyMedia is a logic 1, copper media
is in use. If PhyMedia is a logic 0, fiber media is in use. The
combination of PhyMedia, PhySpeed100, and PhySpeed10 defines
the capabilities of the PHY.
PHYMEDIA PHYSPEED100 PHYSPEED10
0
0
0
0
1
1
1
1
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
36/92
IP100-DS-R03
May 27, 2003
BIT DESCRIPTION
PHY CAPABILITY
Undefined
10BASE-T
100BASE-T
100BASE-T or 10BASE-T
Undefined
10BASE-F
100BASE-F
100BASE-F or 10BASE-F
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
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