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| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 41/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
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IP100
BIT
3
IP100-DS-R03
May 27, 2003
41/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT NAME
RxDMAComplete
R/W
R
BIT DESCRIPTION
Receive DMA Complete. RxDMAComplete is equivalent to the
RxDMAComplete bit in the IntStatus register. RxDMAComplete is
different from the RxDMAComplete bit in RxDMAStatus.
RxDMAComplete is latched once a frame receive DMA transfer has
completed. RxDMAComplete is cleared by acknowledging the
RxDMAComplete bit in the IntStatus register.
TxDMAComplete.
TxDMAComplete
TxDMAComplete bit in IntStatus register. TxDMAComplete is cleared
by acknowledging the TxDMAComplete bit in the IntStatus register.
Reserved for future use.
Receive DMA Halt. If RxDMAHalt is a logic 1, the receive DMA is
halted. RxDMAHalt is self-clearing and writing a 0 is ignored. See
RxDMAHalted to determine the running state of receive DMA.
Receive DMA Resume. If RxDMAResume is a logic 1, the receive
DMA is resumed. RxDMAResume is self-clearing and writing a 0 is
ignored. See RxDMAHalted to determine the running state of
receive DMA.
Transmit DMA Halt. If TxDMAHalt is a logic 1, the transmit DMA is
halted. TxDMAHalt is self-clearing and writing a 0 is ignored. See
TxDMAHalted to determine the running state of transmit DMA.
Transmit DMA Resume. If TxDMAResume is a logic 1, the transmit
DMA is resumed. TxDMAResume is self-clearing and writing a 0 is
ignored. See TxDMAHalted to determine the running state of
transmit DMA.
Reserved for future use.
Transmit DMA in Progress. If TxDMAInProg is a logic 1, a transmit
DMA operation is in progress. TxDMAInProg is primarily used by the
host system in an under run recovery routine. The host system waits
for TxDMAInProg to be a logic 0 before setting the TxReset bit of the
AsicCtrl register to clear the under run condition. Before checking
TxDMAInProg, issue TxDMAHalt.
DMA Halt Busy. DMAHaltBusy indicates that a DMA Halt operation
(TxDMAHalt or RxDMAHalt) is in progress and the host system
should wait for DMAHaltBusy to be cleared before performing other
actions.
Reserved for future use.
Reserved for future use.
Countdown Speed. CountdownSpeed sets the speed at which the
Countdown register decrements. When CountdownSpeed is a logic 1,
the decrement rate of Countdown is once every 3.2 us (i.e. 4 byte
times at 10 Mbps). When CountdownSpeed is a logic 1, the
decrement rate of Countdown is once every 320 ns (i.e. 4 byte times
at 100 Mbps). By setting appropriate CountdownSpeed for the wire
speed, conversions can be made between byte times and counter
values using simple shift operations.
4
TxDMAComplete
R
is
the
same
as
the
7..5
8
Reserved
RxDMAHalt
N/A
W
9
RxDMAResume
W
10
TxDMAHalt
W
11
TxDMAResume
R/W
13..12
14
Reserved
TxDMAInProg
N/A
R
15
DMAHaltBusy
R
16
17
18
Reserved
Reserved
CountdownSpeed
N/A
R/W
R/W
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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