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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 63/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
10.5.3 CarrierSenseErrors
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x74
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
3..0
CarrierSenseErrors
IP100-DS-R03
May 27, 2003
63/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
R/W
R/W
BIT DESCRIPTION
Carrier Sense Errors counts the number of times that the carrier
sense signal (CRS) was de-asserted (a logic 0) during the
transmission of a frame without collision. The carrier sense signal is
not monitored for the purpose of this statistic until after the preamble
and start-of-frame delimiter fields of the Ethernet frame have been
transmitted. CarrierSenseErrors will wrap around to zero after
reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.13.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when CarrierSenseErrors reaches a value of
0xC0. CarrierSenseErrors is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of CarrierSenseErrors also clears the register.
Reserved for future use.
7..4
Reserved
R/W
10.5.4 FramesAbortedDueToXSColls
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7b
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
7..0
FramesAborted-
DueToXSColls
R/W
R/W
BIT DESCRIPTION
Frames Aborted Due to Excess Collisions counts the number of
frames which are not transmitted successfully due to excessive
collisions. FramesAbortedDueToXSColls will wrap around to zero
after reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.11.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesAbortedDueToXSColls reaches a
value of 0xC0. FramesAbortedDueToXSColls is enabled by writing
a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of FramesAbortedDueToXSColls also clears the register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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