
IP100
PIN DESCRIPTIONS (continued)
PIN NAME
PIN TYPE
PIN DESCRIPTION
PCI INTERFACE
PERRN
IN/OUT
Parity Error, asserted LOW. The IP100 asserts PERRN when it checks and
detects a bus parity errors. When it is generating PAR output, the IP100
monitors for any reported parity error on PERRN.
System Error, asserted LOW.
Power Detect. The IP100 detects PCI bus power supply loss when VDET is LOW.
EEPROM INTERFACE
EEPROM Chip Select. EECS is asserted by the IP100 to access the
EEPROM. EECS is connected directly to the chip select input of the EEPROM
device.
EEPROM Serial Clock. EESK is an output connected directly to the clock
input of the EEPROM device.
EEPROM Data Input. EEDI is an output connected directly to the data input of
the EEPROM device.
EEPROM Data Output. EEDO is an input connected directly to the data output
of the EEPROM device.
EXPANSION ROM INTERFACE
Expansion ROM Address Bus. EA is the expansion ROM address (see
ExpRomAddr and ExpRomData registers).
Expansion ROM Data Bus. ED is the expansion ROM data bus (see
ExpRomAddr and ExpRomData registers).
Expansion ROM Write Enable. EWEN is the expansion ROM write enable
signal during accesses to the expansion ROM (see ExpRomAddr and
ExpRomData registers).
Expansion ROM Output Enable. EOEN is the expansion ROM output enable
signal during accesses to the expansion ROM (see ExpRomAddr and
ExpRomData registers).
Expansion ROM Chip Select. ECSN is asserted by the IP100 to access the
Expansion ROM. ECSN is connected directly to the chip select input of the
Expansion ROM device.
LED DRIVERS
Speed Status LED. LEDSPDN is the speed status LED driver. The speed
status LED driver is LOW when the link speed is 100Mbps, and HIGH when
the link speed is 10Mbps. Additional functionality of the speed status LED
signal is based on the LEDMode bit of the AsicCtrl register.
Duplex Status LED. LEDDPLXN is the duplex status LED driver. The duplex
status LED driver is LOW when the link is full duplex, and HIGH when the link
is half duplex. Additional functionality of the speed status LED signal is based
on the LEDMode bit of the AsicCtrl register.
SERRN
VDET
OUTPUT
INPUT
EECS
OUTPUT
EESK
OUTPUT
EEDI
OUTPUT
EEDO
INPUT
EA
[15..0]
ED
[7..0]
EWEN
OUTPUT
IN/OUT
OUTPUT
EOEN
OUTPUT
ECSN
OUTPUT
LEDSPDN
OUTPUT
LEDDPLXN
OUTPUT
TABLE 2 : IP100 Pin Descriptions
Copyright 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
May 27, 2003
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IP100-DS-R03