參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁(yè)數(shù)： 7/92頁(yè)
文件大?。?/td> 2801K
代理商： IP100
IP100
PIN DESCRIPTIONS (continued)
PIN NAME
PIN TYPE
PIN DESCRIPTION
LED DRIVERS
LEDPWRN
OUTPUT
Power Status LED. LEDPWRN is the power status LED driver. The
functionality of the power status LED signal is based on the LEDMode bit of
the AsicCtrl register.
Link Status LED. LEDLNKN is the link status LED driver. The functionality of the
link status LED signal is based on the LEDMode bit of the AsicCtrl register.
MDI
Receive input. When in 100BASE-TX mode, this receives MLT3 data from the
isolation transformer. When in 100BASE-FX mode, this is a PECL input.
Receive input. When in 100BASE-TX mode, this receives MLT3 data from the
isolation transformer. When in 100BASE-FX mode, this is a PECL input.
Transmit output. When in 100BASE-TX mode, this is an MLT-3 driver. When
in 100BASE-FX mode, this is a PECL driver.
Transmit output. When in 100BASE-TX mode, this is an MLT-3 driver. When
in 100BASE-FX mode, this is a PECL driver.
Fiber optic signal detect. For 100BASE-FX applications, FSD is connected to
the signal detect output pin of a fiber optic module at PECL level. Connecting
this pin to GND will force the IP100 in the 100BASE-TX mode.
For FX usage, this pin can be left floating. For UTP application, its purpose is
to provide a common mode reference voltage to the transmit transformer and
it should connect this pin to the center tap of the transmit transformer. For EMI
consideration, it is also suggested to place a bead (100Mhz) between the
center tap of the transformer and the VREF pin. If the noise is still disturbing
the signals, a 39pF capacitor should also be considered.
MISCELLANEOUS
25MHz Crystal Oscillator Input. The external 25MHz crystal and capacitor is
connected to the on-chip crystal oscillator circuit through X25I input.
Alternately, X25I can be driven by an external clock source.
25MHz Crystal Oscillator Output. The external crystal and capacitor is also
connected to the output of the on-chip crystal oscillator circuit through X25O. When
X25I is driven by an external clock source, X25O should be left unconnected.
Band Gap Resistor. Connect a 6.2kohm, 1% resister between ISET and GND.
Voltage regulator input. The internal 2.5V voltage regulator requires a 2N2905
type, PNP transistor be connected between REGIN and REGOUT.
Voltage regulator output. The internal 2.5V voltage regulator requires a
2N2905 type, PNP transistor be connected between REGIN and REGOUT.
Analog Test. Do not connect for normal operation.
Digital Test. Do not connect for normal operation.
Test. Enables the IP100 test modes.
POWER AND GROUND
+3.3 volt I/O power supply.
+2.5 volt digital logic power supply.
+2.5 volt analog power supply.
Power return.
Power return.
LEDLNKN
OUTPUT
RXP
INPUT
RXN
INPUT
TXP
OUTPUT
TXN
OUTPUT
FSD
INPUT
VREF
ANALOG
X25I
OSCIN
X25O
OSCOUT
ISET
REGIN
ANALOG
ANALOG
REGOUT
ANALOG
AOUT
DOUT
TEST
IN/OUT
IN/OUT
INPUT
VCCH
VCCL
VCCA
GND
AGND
POWER
POWER
POWER
GROUND
GROUND
TABLE 2 : IP100 Pin Descriptions
IP100-DS-R03
May 27, 2003
7/92
Copyright 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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IP1000ALF-DS-R03 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip
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