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參數(shù)資料
| 型號(hào)： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 79/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
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IP100
10.6.20 PowerMgmtCap
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x52
Default Value ................ 0x7602
Width ............................ 16 bits
PowerMgmtCap provides information about the IP100’s power management capabilities. Several bits are loaded
from the EEPROM during auto-initialization.
BIT
BIT NAME
R/W
2..0
Versi on
R
Version. Version is set to 0x2, indicating PCI Bus Power
Management Specification Revision 1.1.
3
Reserved
N/A
Reserved for future use.
4
Vaux
R
Auxiliary Voltage. If Vaux is a logic 1, auxiliary power via the PCI
Bus is required from the system to support PME in the D3cold state.
If Vaux is a logic 0, auxiliary power is supplied from elsewhere (i.e.
not from the PCI Bus) to support PME in the D3cold state.
8..5
Reserved
N/A
Reserved for future use.
9
D1Support
R
D1 Power State Support. When D1Support is a logic 1, the IP100
supports the D1 power state. D1Support is loaded from the
ConfigParm field of an EEPROM during auto initialization of the
IP100.
10
D2Support
R
D2 Power State Support. When D2Support is a logic 1, the IP100
supports the D2 power state. D2Support is loaded from the
ConfigParm field of an EEPROM during auto initialization of the
IP100.
15..11
PmeSupport
R
Power Management Event Support. PmeSupport indicates the power
states from which the IP100 is able to generate a power management
event by asserting the WAKE signal. Each bit corresponds to a power
state. A logic 1 in a particular bit position indicates that events can be
generated from the indicated power state.
IP100-DS-R03
May 27, 2003
79/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT DESCRIPTION
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
POWER MANAGEMENT
EVENT MAY BE
GENERATED FROM STATE
D0
D1
D2
D3Hot
D3Cold
x
x
x
x
1
x
x
x
1
x
x
x
1
x
x
x
1
x
x
x
1
x
x
x
x
The IP100 hard-wires bit 11 to zero and bit 14 to one. The values of bits
12,13, and 15 are determined by bits 4, 5 and 3 respectively from the
EEPROM ConfigParm.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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