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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 42/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
42/92
IP100-DS-R03
May 27, 2003
BIT
19
BIT NAME
CountdownMode
R/W
R/W
BIT DESCRIPTION
Countdown Mode. CountdownMode controls the operating mode of
the Countdown register. With CountdownMode is a logic 0,
Countdown begins decrementing as soon as a nonzero value is
written to Countdown. With CountdownMode is a logic 1, Countdown
will not begin decrementing until the TxDMAComplete bit in the
IntStatus register is a logic 1. See the Countdown register definition
for more information on the Countdown modes.
PCI MWI Command Disable. If Setting MWIDisable is a logic 1, the
IP100 will not use the Memory Write Invalidate (MWI) PCI command.
Reserved for future use.
Receive DMA Overrun Frame. If RxDMAOverrunFrame is a logic 0,
receive DMA will discard receive overrun frames without transferring
them to the host system. WhenRxDMAOverrunFrame is a logic 1,
receive DMA will transfer overrun frames to the host system.
Overrun frames are any frame which is received while the receive
FIFO is full.
Countdown Interrupt Enable. CountdownIntEnable specifies whether
expiration of the Countdown register will generate an interrupt. If
CountdownIntEnable is a logic 0, Countdown expiration will not set
the IntRequested bit of the IntStatus register. IfCountdownIntEnable
is a logic 1, expiration of Countdown will set the IntRequested bit of
the IntStatus register. The state of CountdownIntEnable is set by the
IP100. CountdownIntEnable is cleared automatically by if the
IntRequested bit in the IntStatus register is a logic 1, or when a zero
value is written to Countdown. CountdownIntEnable is set implicitly
when a non-zero value is written into Countdown. This allows the host
to write a non-zero value to Countdown and an interrupt will be
generated in a corresponding amount of time. By writing a zero value
to Countdown the host can suppress interrupts.
Reserved for future use.
Bus Target Abort. TargetAbort is a logic 1 when the IP100
experiences a target abort sequence when operating as a bus
master. TargetAbort indicates a fatal error, and must be cleared
before further transmit DMA or receive DMA operation can proceed.
TargetAbortt is cleared via the GlobalReset, and DMA bits of the
AsicCtrl register.
Bus Master Abort. MasterAbort is a logic 1 when the IP100
experiences a master abort sequence when operating as a bus
master. MasterAbort indicates a fatal error, and must be cleared
before further transmit DMA or receive DMA operation can proceed.
MasterAbortt is cleared via the GlobalReset, and DMA bits of the
AsicCtrl register.
20
MWIDisable
R/W
21
22
Reserved
RxDMAOverrun-
Frame
N/A
R/W
23
CountdownIntEnable
R
29..24
30
Reserved
TargetAbort
N/A
R
31
MasterAbort
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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