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參數(shù)資料
| 型號(hào)： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 64/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
10.5.5 FramesLostRxErrors
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x79
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
7..0
FramesLostRxErrors
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
64/92
IP100-DS-R03
May 27, 2003
R/W
R/W
BIT DESCRIPTION
Frames Lost Due to Receive Errors is a count of the number of
frames that should have been received (the destination address
matched the filter criteria) but experienced a receive FIFO overrun
error (the receive FIFO does not have enough free space to store
the received data). FramesLostRxErrors only includes overruns that
become apparent to the host system, and does not include frames
that are completely ignored due to a completely full receive FIFO at
the beginning of frame reception. FramesLostRxErrors will wrap
around to zero after reaching 0xFF. See IEEE 802.3 Clause
30.3.1.1.15.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesLostRxErrors reaches a value of
0xC0. FramesLostRxErrors is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of FramesLostRxErrors also clears the register.
10.5.6 FramesReceivedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x72
Default .......................... 0x0000
Width ............................ 16 bits
BIT
BIT NAME
7..0
FramesReceivedOk
R/W
R/W
BIT DESCRIPTION
Frames Received OK is the count of the number of frames that are
successfully received. FramesReceivedOk does not include frames
received with frames too long, FCS, length or alignment errors, or
frames lost due to internal MAC sublayer error (i.e. overrun).
FramesReceivedOk will wrap around to zero after reaching 0xFFFF.
See IEEE 802.3 Clause 30.3.1.1.5.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesReceivedOk reaches a value of
0xC0. FramesReceivedOk is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of FramesReceivedOk also clears the register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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