參數(shù)資料
型號(hào): AM79C965KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝: PLASTIC, QFP-160
文件頁(yè)數(shù): 101/220頁(yè)
文件大?。?/td> 1197K
代理商: AM79C965KCW
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P R E L I M I N A R Y
AMD
19
Am79C965
Pin Connections to VDD or VSS
Several pins may be connected to VDD or VSS for various
application options. Some pins are required to be con-
nected to VDD or VSS in order to set the controller into a
particular mode of operation, while other pins might be
connected to VDD or VSS if that pin’s function is not imple-
mented in a specific application. Table 5 shows which
pins
require a connection to VDD or VSS, and which pins
may
optionally be connected to VDD or VSS because the
application does not support that pin’s function. The
table also shows whether or not the connections need to
be resistive.
VESA VL-Bus Interface
ADR2–ADR31
Address Bus
Input/Output
Address information which is stable during a bus opera-
tion, regardless of the source. When the PCnet-32 con-
troller is Current Master, A2–A31 will be driven. When
the PCnet-32 controller is not Current Master, the
A2–A31 lines are continuously monitored to determine if
an address match exists for I/O slave transfers.
ADS
Address Status
Input/Output
When driven LOW, this signal indicates that a valid bus
cycle definition and address are available on the M/
IO,
D/
C, W/R and A2–A31 pins of the local bus interface. At
that time, the PCnet-32 controller will examine the com-
bination of M/
IO, D/C, W/R, and the A2–A31 pins to
determine if the current access is directed toward the
PCnet-32 controller.
ADS will be driven LOW when the PCnet-32 controller
performs a bus master access on the local bus.
BE0–BE3
Byte Enable
Input/Output
These signals indicate which bytes on the data bus are
active during read and write cycles. When
BE3 is active,
the byte on DAT31–DAT24 is valid.
BE2–BE0 active
indicate valid data on pins DAT23–DAT16, DAT15–
DAT8, DAT7–DAT0, respectively. The byte enable sig-
nals are outputs for bus master and inputs for bus slave
operations.
BLAST
Burst Last
Output
When the
BLAST signal is asserted, then the next time
that
BRDY or RDYRTN is asserted, the burst cycle is
complete.
BRDY
Burst Ready
Input/Output
BRDY functions as an input to the PCnet-32 controller
during bus master cycles. When
BRDY is asserted dur-
ing a master cycle, it indicates to the PCnet-32 controller
that the target device is accepting burst transfers. It also
serves the same function as
RDYRTN does for non-
burst accesses. That is, it indicates that the target de-
vice has accepted the data on a master write cycle, or
that the target device has presented valid data onto the
bus during master read cycles.
Table 5. Pin Connections to Power/Ground
Resistive
Supply
Connection
Recommended
Pin Name
Pin No
Strapping
to Supply
Resistor Size
LED2/SRDCLK
2
Required
324
in series with LED, or 10 K
without LED
LBS16
25
Optional
Required
10 K
VLBEN
31
Required
Optional
NA
WBACK
54
Optional
Required
10 K
LREQI/TDO
100
Optional
Required
10 K
JTAGSEL
106
Required
Optional
NA
EEDO/LEDPRE3/SRD
152
Optional
Required
10 K
LB/
VESA
153
Required
Optional
NA
EEDI/
LNKST
154
Optional
Required
324
in series with LED, or 10 K
without LED
EESK/LED1/SFBD
155
Required
324
in series with LED, or 10 K
without LED
SLEEP
156
Optional
Required
10 K
All Other Pins
Optional
Required
10 K
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