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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 75/220頁 |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
166
Am79C965
ESK has no effect on the EESK
pin unless the PREAD bit is set to
ZERO and the EEN bit is set to
ONE.
ESK
is
reset
to
ONE
by
H_RESET and is unaffected by
S_RESET or STOP.
0
EDI/EDO
EEPROM Data In / EEPROM
Data Out. Data that is written to
this bit will appear on the EEDI
output of the microwire interface,
except when the PREAD bit is set
to ONE or the EEN bit is set to
ZERO. Data that is read from this
bit reflects the value of the EEDO
input of the microwire interface.
EDI/EDO has no effect on the
EEDI pin unless the PREAD bit is
set to ZERO and the EEN bit is
set to ONE.
EDI/EDO is reset to ZERO by
H_RESET and is unaffected by
S_RESET or STOP.
BCR20: Software Style
Bit
Name
Description
This register is an alias of the lo-
cation CSR58. Accesses to/from
this register are equivalent to ac-
cesses to CSR58.
31-10
RES
Reserved locations. Written as
ZEROs and read as undefined.
9
CSRPCNET
CSR PCnet-ISA configuration
bit. When set, this bit indicates
that the PCnet-32 controller reg-
ister bits of CSR4 and CSR3 will
map directly to the CSR4 and
CSR3 bits of the PCnet-ISA
(Am79C960)
device.
When
cleared, this bit indicates that
PCnet-32 controller register bits
of CSR4 and CSR3 will map di-
rectly to the CSR4 and CSR3 bits
of
the
ILACC
(Am79C900)
device.
The value of CSRPCNET is
determined by the PCnet-32 con-
troller. CSRPCNET is read only
by the host.
The PCnet-32 controller uses the
setting of the Software Style reg-
ister (BCR20[7:0]) to determine
the value for this bit.
CSRPCNET is set by H_RESET
and is not affected by S_RESET
or STOP.
8
SSIZE32
Software Size 32 bits. When set,
this
bit
indicates
that
the
PCnet-32 controller utilizes AMD
79C900 (ILACC) software struc-
tures. In particular, Initialization
Block and Transmit and Receive
descriptor bit maps are affected.
When cleared, this bit indicates
that the PCnet-32 controller util-
izes AMD PCnet-ISA software
structures.
Note: Regardless of
the setting of SSIZE32, the In-
itialization Block must always be-
gin on a double-word boundary.
The value of SSIZE32 is deter-
mined by the PCnet-32 control-
ler. SSIZE32 is read only by the
host.
The PCnet-32 controller uses the
setting of the Software Style reg-
ister
(BCR20[7:0]/CSR58[7:0])
to determine the value for this bit.
SSIZE32 is cleared by H_RESET
and is not affected by S_RESET
or STOP.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32 bit address
bus during master accesses initi-
ated by the PCnet-32 controller.
This action is required, since the
16-bit software structures speci-
fied by the SSIZE32=0 setting
will yield only 24 bits of address
for PCnet-32 controller bus mas-
ter accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to the PCnet-32 controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the PCnet-32
controller for performing master
accesses.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address pins. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
Note that the setting of the
SSIZE32 bit has no effect on the
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit.
7-0
SWSTYLE
Software
Style
register.
The
value in this register determines
the “style” of I/O and memory
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