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| 型號(hào)： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 220/220頁(yè) |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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P R E L I M I N A R Y
AMD
99
Am79C965
18219B-39
XMT
Filter
RCV
Filter
RJ45
Connector
Filter &
Transformer
Module
PCnet-32
TD+
TD-
RD+
RD-
1
2
3
6
61.9
422
61.9
422
100
1.21 K
1:1
TXD+
TXP+
TXD-
TXP-
RXD+
RXD-
Figure 32. 10BASE-T Interface Connection
IEEE 1149.1 Test Access Port Interface
An IEEE 1149.1 compatible boundary scan Test Access
Port is provided for board level continuity test and diag-
nostics. All digital input, output and input/output pins are
tested. Analog pins, including the AUI differential driver
(DO
±) and receivers (DI±, CI±), and the crystal input
(XTAL1/XTAL2) pins, are tested. The T-MAU drivers
TXD
±, TXP± and receiver RXD± are also tested.
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the PCnet-32
controller.
Boundary Scan Circuit
The boundary scan test circuit requires four pins (TCK,
TMS, TDI and TDO), defined as the Test Access Port
(TAP). It includes a finite state machine (FSM), an in-
struction register, a data register array, and a power-on
reset circuit. Internal pull-up resistors are provided for
the TDI, TCK, and TMS pins. The TCK pin must not be
left unconnected. The boundary scan circuit remains ac-
tive during Sleep.
TAP FSM
The TAP engine is a 16-state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. This
FSM is in its reset state at power-up or after H_RESET.
An independent power-on reset circuit is provided to en-
sure the FSM is in the TEST_LOGIC_RESET state at
power-up.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST, and SAMPLE instructions), three
additional instructions (IDCODE, TRIBYP and SET-
BYP) are provided to further ease board-level testing.
All unused instruction codes are reserved. See Table 28
for a summary of supported instructions.
Instruction Register and Decoding Logic
After H_RESET or S_RESET or STOP, the IDCODE
instruction is always invoked. The decoding logic gives
signals to control the data flow in the DATA registers
according to the current instruction.
Boundary Scan Register (BSR)
Each BSR cell has two stages. A flip-flop and a latch are
used for the SERIAL SHIFT STAGE and the PARALLEL
OUTPUT STAGE, respectively.
Table 28. IEEE 1149.1 Supported Instruction Summary
Instruction
Selected
Instruction
Name
Description
Data Reg
Mode
Code
EXTEST
External Test
BSR
Test
0000
IDCODE
ID Code Inspection
ID REG
Normal
0001
SAMPLE
Sample Boundary
BSR
Normal
0010
TRIBYP
Force Tristate
Bypass
Normal
0011
SETBYP
Control Boundary To 1/0
Bypass
Test
0100
BYPASS
Bypass Scan
Bypass
Normal
1111
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