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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 7/220頁 |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
104
Am79C965
APROM locations. The PCnet-32 controller may or may
not produce an
LDEV and a RDY signal in response to
such accesses, but data will be undefined.
Accesses of non-word quantities to any I/O resource are
not allowed while in WIO mode,
with the exception of
byte reads from the APROM locations. PCnet-32 con-
troller may or may not produce an
LDEV and will not
produce a
RDY signal in response to such accesses,
but data will be undefined.
The Vendor Specific Word (VSW) is not implemented by
the PCnet-32 controller. This particular I/O address is
reserved for customer use and will not be used by future
AMD Ethernet controller products. If more than one
Vendor Specific Word is needed, it is suggested that the
VSW location should be divided into a VSW Register
Address Pointer (VSWRAP) at one location (e.g.
VSWRAP at byte location 18h) and a VSW Data Port
(VSWDP) at the other location (e.g. VSWDP at byte lo-
cation 19h). Alternatively, the system may capture RAP
data accesses in parallel with the PCnet-32 controller
and therefore share the PCnet-32 controller RAP to al-
low expanded VSW space. PCnet-32 controller will not
respond to access to the VSW I/O address.
DWIO I/O Resource Map
When the PCnet-32 controller I/O space is mapped as
Double Word I/O, then all of the resources that are allot-
ted to the PCnet-32 controller occur on double word
boundaries that are offset from the PCnet-32 controller
I/O Base Address as shown in Table 33.
Table 33. Double Word I/O Mapping
Offset
No. of
(Hex)
Bytes
Register
0
4
Address PROM
4
Address PROM
8
4
Address PROM
C
4
Address PROM
10
4
RDP
14
4
RAP (shared by RDP and BDP)
18
4
Reset Register
1C
4
BDP
When PCnet-32 controller I/O space is Double Word
mapped, all I/O resources fall on double word bounda-
ries. Address PROM resources are double word quanti-
ties in DWIO mode. RDP, RAP and BDP contain only
two bytes of valid data. The other two bytes of these
resources are reserved for future use. The reserved
bits must be written as zeros, and when read, are con-
sidered
undefined.
Accesses to non-double word address boundaries are
not allowed while in DWIO mode. The PCnet-32 control-
ler may or may not produce an
LDEV and a RDY signal
in response to such accesses, but data will be
undefined.
Accesses of less than 4 bytes to any I/O resource are
not allowed while in DWIO mode (i.e. PCnet-32 control-
ler will not respond to such accesses. PCnet-32 control-
ler will not produce an
LDEV and a RDY signal in
response to such accesses), but data will be undefined.
A double word write access to the RDP offset of 10h will
automatically program DWIO mode.
Note that in all cases when I/O resource width is defined
as 32 bits, the upper 16 bits of the I/O resource is re-
served and written as ZEROs and read as undefined,
except for the APROM locations and CSR88.
DWIO mode is exited by asserting the RESET pin. As-
sertion of S_RESET or setting the STOP bit of CSR0 will
have no effect on the DWIO mode setting.
I/O Space Comments
The following statements apply to both WIO and DWIO
mapping:
The RAP is shared by the RDP and the BDP.
The PCnet-32 controller does not respond to any ad-
dresses outside of the offset range 0h-17h when
DWIO = 0 or 0h-1F when DWIO = 1. I/O offsets 18h
through 1Fh are not used by the PCnet-32 controller
when programmed for DWIO = 0 mode. Locations 1Ah
through 1Fh are reserved for future AMD use and there-
fore should not be implemented by the user if upward
compatibility to future AMD devices is desired.
Note that Address PROM accesses do not directly ac-
cess the EEPROM, but are redirected to a set of shadow
registers on board the PCnet-32 controller that contain a
copy of the EEPROM contents that was obtained during
the automatic EEPROM read operation that follows the
RESET operation.
PCnet-32 Controller I/O Base Address
The I/O Base Address Registers (BCR16 and BCR17)
will reflect the current value of the base of the PCnet-32
controller I/O address space. BCR16 contains the lower
16 bits of the 32-bit I/O base address for the PCnet-32
controller. BCR17 contains the upper 16 bits of the
32-bit I/O base address for the PCnet-32 controller. This
set of registers is both readable and writeable by the
host. The value contained in these registers is affected
through three means:
1. Immediately
following the H_RESET operation, the
I/O Base Address will be determined by the
EEPROM read operation. During this operation, the
I/O Base Address register will become programmed
with the value of the I/O Base Address field of the
EEPROM.
2. If no EEPROM exists, or if an error is detected in the
EEPROM data, then the PCnet-32 controller will en-
ter Software Relocatable Mode. While in this
mode, the PCnet-32 controller will not respond to
any I/O accesses directly. However, the PCnet-32
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
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