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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 209/220頁 |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
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P R E L I M I N A R Y
AMD
89
Am79C965
A typical receive poll is the product of the following con-
ditions:
1. PCnet-32 controller does not possess ownership of
the current RDTE and the poll time has elapsed and
RXON = 1, or
2. PCnet-32 controller does not possess ownership
of the next RDTE the poll time has elapsed and
RXON = 1.
If RXON = 0 the PCnet-32 controller will never poll
RDTE locations.
The ideal system should always have at least one RDTE
available for the possibility of an unpredictable receive
event. (This condition is not a requirement. If this condi-
tion is not met, it simply means that frames will be
missed by the system because there was no buffer
space available.) But the typical system usually has at
least one or two RDTEs available for the possibility of an
unpredictable receive event. Given that this condition is
satisfied, the current and next RDTE polls are rarely
seen and hence, the typical poll operation simply con-
sists of a check of the status of the current TDTE. When
there is only one RDTE (because the RLEN was set to
zero), then there is no “next RDTE” and ownership of
“next RDTE” cannot be checked. If there is at least one
RDTE, the RDTE poll will rarely be seen and the typical
poll operation simply consists of a check of the current
TDTE.
A typical transmit poll is the product of the following
conditions:
1. PCnet-32 controller does not possess ownership of
the current TDTE and
DPOLL = 0 and
TXON = 1 and
the poll time has elapsed, or
2. PCnet-32 controller does not possess ownership of
the current TDTE and
DPOLL = 0 and
TXON = 1 and
a frame has just been received, or
3. PCnet-32 controller does not possess ownership of
the current TDTE and
DPOLL = 0 and
TXON = 1 and
a frame has just been transmitted.
Setting the TDMD bit of CSR0 will cause the microcode
controller to exit the poll counting code and immediately
perform a polling operation. If RDTE ownership has not
been previously established, then an RDTE poll will be
performed ahead of the TDTE poll. If the microcode is
not executing the poll counting code when the TDMD bit
is set, then the demanded poll of the TDTE will be de-
layed until the microcode returns to the poll count-
ing code.
The user may change the poll time value from the de-
fault of 65,536 BCLK periods by modifying the value
in the Polling Interval register (CSR47). Note that if a
non-default value is desired, then a strict sequence of
setting the INIT bit in CSR0, waiting for IDON (CSR0[8]),
then writing to CSR47, and then setting STRT in CSR0
must be observed, otherwise the default value will not
be overwritten. See the CSR47 section for details.
Transmit Descriptor Table Entry (TDTE)
If, after a TDTE access, the PCnet-32 controller finds
that the OWN bit of that TDTE is not set, then the
PCnet-32 controller resumes the poll time count and
reexamines the same TDTE at the next expiration of the
poll time count.
If the OWN bit of the TDTE is set, but STP = 0, the
PCnet-32 controller will immediately request the bus in
order to reset the OWN bit of this descriptor. (This condi-
tion would normally be found following a LCOL or RE-
TRY error that occurred in the middle of a transmit
frame chain of buffers.) After resetting the OWN bit of
this descriptor, the PCnet-32 controller will again imme-
diately request the bus in order to access the next TDTE
location in the ring.
If the OWN bit is set and the buffer length is 0, the OWN
bit will be reset. In the LANCE the buffer length of 0 is
interpreted as a 4096-byte buffer. It is acceptable to
have a 0 length buffer on transmit with STP = 1 or
STP = 1
and ENP = 1. It is not acceptable to have 0
length buffer with STP = 0 and ENP =1.
If the OWN bit is set and the start of packet (STP) bit is
set, then microcode control proceeds to a routine that
will enable transmit data transfers to the FIFO. The
PCnet-32 controller will look ahead to the next transmit
descriptor after it has performed at least one transmit
data transfer from the first buffer. (More than one trans-
mit data transfer may possibly take place, depending
upon the state of the transmitter.) The contents of TMD0
and TMD1 will be stored in Next Xmt Buffer Address
(CSR64 and CSR65), Next Xmt Byte Count (CSR66)
and Next Xmt Status (CSR67) regardless of the state of
the OWN bit. This transmit descriptor look-ahead opera-
tion is performed only once.
If the PCnet-32 controller does not own the next TDTE
(i.e. the second TDTE for this frame), then it will com-
plete transmission of the current buffer and then update
the status of the current (first) TDTE with the BUFF and
UFLO bits being set. This will cause the transmitter to be
disabled (CSR0, TXON=0). The PCnet-32 controller will
have to be re-initialized to restore the transmit function.
The situation that matches this description implies that
the system has not been able to stay ahead of the
PCnet-32 controller in the transmit descriptor ring and
therefore, the condition is treated as a fatal error. (To
avoid this situation, the system should always set the
transmit chain descriptor own bits in reverse order.)
If the PCnet-32 controller does own the second TDTE in
a chain, it will gradually empty the contents of the first
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
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