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| 型號(hào)： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 8/220頁(yè) |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
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P R E L I M I N A R Y
AMD
105
Am79C965
controller will snoop accesses on the system bus.
When the PCnet-32 controller detects a specific
sequence of four write accesses to I/O address
378h, then the PCnet-32 controller will assume that
the software is attempting to relocate the PCnet-32
controller. On eight subsequent write accesses to
I/O address 378h, the PCnet-32 controller will accept
the data on the bus as a new I/O Base Address and
other programming information, and it will leave
Software Relocatable Mode. At this point, the
PCnet-32 controller will begin responding to I/O ac-
cesses directly.
While the PCnet-32 controller is in software
relocatable mode, if the LED2 pin is pulled LOW,
then the SRMA24 mode is entered and only the
lower 24 bits of address are matched to 378h.
3. The I/O Base Address Registers may be directly writ-
ten to, provided that the PCnet-32 controller is not
currently in the Software Relocatable Mode.
Software Relocation of I/O Resources
In order to allow for jumperless Ethernet implementa-
tions, the I/O Base Address register value will be auto-
matically altered by the PCnet-32 controller during an
EEPROM read operation. In this case, the value of the
I/O Base Address for the PCnet-32 controller will be di-
rectly dependent upon the value of the BCR16 and
BCR17 fields that are stored in the EEPROM. If no
EEPROM exists and an EEPROM read is attempted,
then the PCnet-32 controller will enter Software
Relocatable Mode.
Software Relocatable Mode
While in Software Relocatable Mode, the PCnet-32 con-
troller will not respond to any access on the system bus.
However, the PCnet-32 controller will snoop any I/O
write accesses that may be present. The PCnet-32 con-
troller will watch for a specific sequence of accesses in
order to determine a value for the I/O Base Address
Registers. Specifically, the PCnet-32 controller will wait
for a sequence of 12 uninterrupted byte-write accesses
to I/O address 378h.
The 12 byte-write accesses must occur without inter-
vening I/O accesses to other locations, and they must
contain the data in the order shown in Table 34.
BE0 is required to be active during all Software
Relocatable Mode snoop accesses.
BE3–BE1 may
have any value during Software Relocatable Mode
snoop accesses.
Table 34. I/O Base Address Write
Sequence in SRM
ASCII
I/O Address
D[7:0]*
Inter–
Access No.
(Hex)
pretation
1
0000 0378
41
A
2
0000 0378
4D
M
3
0000 0378
44
D
4
0000 0378
01
NA
5
0000 0378
IOBASEL[7:0]
NA
6
0000 0378
IOBASEL[15:8]
NA
7
0000 0378
IOBASEU[7:0]
NA
8
0000 0378
IOBASEU[15:8]
NA
9
0000 0378
BCR2[7:0]
NA
10
0000 0378
BCR2[15:8]
NA
11
0000 0378
BCR21[7:0]
NA
12
0000 0378
BCR21[15:8]
NA
*Note that D[31:8] are don’t care, since the accesses are
required to one byte in width.
Immediately following the 12th write access in the se-
quence, the PCnet-32 controller will leave Software
Relocatable Mode, and it will then respond to I/O ac-
cesses to the 32 bytes of I/O space that begins at the I/O
Base Address location.
Note that in Figure 33 (Software Relocatable Mode
Snoop Accesses), the data that is accepted by the
PCnet-32 controller will always be the data that is pre-
sented during the first T2 cycle, regardless of the state of
the
RDYRTN input.
Since the PCnet-32 controller will not respond to the
Software Relocatable Mode snoop accesses, some
other device must drive the
RDYRTN signal during
these accesses. In a typical PC environment, these I/O
accesses will be directed toward the data port of a paral-
lel port. Therefore, the
RDYRTN will typically be gener-
ated by the parallel port controller. In systems in which
the parallel port device does not exist, or is at a different
location, the 378h accesses will go unclaimed by any
device on the local bus or on the expansion bus. In this
case, the chipset will typically terminate the access by
providing the
RDYRTN signal after some access-time-
out counter has elapsed.
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