參數(shù)資料
型號(hào)： AM79C965KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 81/220頁(yè)
文件大?。?/td> 1197K
代理商： AM79C965KCW
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P R E L I M I N A R Y
AMD
171
Am79C965
Table 60. Receive Descriptor (SSIZE32 =1)
PCnet-32
Descriptor
Designation
Address
Bits 31-24
Bits 23-16
Bits 15-8
Bits 7-0
Bits 31-0
CRDA+00
*NA
RMD1[7:0]
RMD0[15:8]
RMD0[7:0]
RMD0
CRDA+04
RMD1[15:8]
*NA
RMD2[15:8]
RMD2[7:0]
RMD1
CRDA+08
*NA
RMD3[15:8]
RMD3[7:0]
RMD2
CRDA+0C
*NA
RMD3
LANCE/PCnet-ISA
Descriptor Designation
*NA = These 8 bits do not exist in any LANCE descriptor.
The Receive Descriptor Ring Entries (RDREs) are com-
posed of four receive message descriptors (RMD0–
RMD3). Together they contain the following information:
s The address of the actual message data buffer in
user (host) memory.
s The length of that message buffer.
s Status information indicating the condition of the
buffer. The eight most significant bits of RMD1
(RMD1[31:24]) are collectively termed the STATUS
of the receive descriptor.
RMD0
Bit
Name
Description
31-0
RBADR
RECEIVE BUFFER ADDRESS.
This field contains the address of
the receive buffer that is associ-
ated with this descriptor.
RMD1
Bit
Name
Description
31
OWN
This bit indicates that the de-
scriptor entry is owned by the
host
(OWN=0)
or
by
the
PCnet-32 controller (OWN=1).
The PCnet-32 controller clears
the OWN bit after filling the buffer
pointed to by the descriptor entry.
The host sets the OWN bit after
emptying the buffer. Once the
PCnet-32 controller or host has
relinquished
ownership
of
a
buffer, it must not change any
field in the descriptor entry.
30
ERR
ERR is the OR of FRAM, OFLO,
CRC, or BUFF. ERR is set by the
PCnet-32 controller and cleared
by the host.
29
FRAM
FRAMING
ERROR
indicates
that the incoming frame con-
tained a non-integer multiple of
eight bits and there was an FCS
error. If there was no FCS error
on the incoming frame, then
FRAM will not be set even if there
was a non integer multiple of
eight bits in the frame. FRAM is
not valid in internal loopback
mode. FRAM is valid only when
ENP is set and OFLO is not.
FRAM is set by the PCnet-32
controller and cleared by the
host.
28
OFLO
OVERFLOW error indicates that
the receiver has lost all or part of
the incoming frame, due to an in-
ability to store the frame in a
memory buffer before the inter-
nal FIFO overflowed. OFLO is
valid only when ENP is not set.
OFLO is set by the PCnet-32
controller and cleared by the
host.
27
CRC
CRC indicates that the receiver
has detected a CRC (FCS) error
on the incoming frame. CRC is
valid only when ENP is set and
OFLO is not. CRC is set by the
PCnet-32 controller and cleared
by the host.
26
BUFF
BUFFER ERROR is set any time
the PCnet-32 controller does not
own the next buffer while data
chaining a received frame. This
can occur in either of two ways:
1) The OWN bit of the next
buffer is zero.
2) FIFO overflow occurred be-
fore the PCnet-32 controller
received
the
STATUS
(RMD1[31:24]) of the next de-
scriptor.
If a Buffer Error occurs, an Over-
flow Error may also occur inter-
nally in the FIFO, but will not be
reported in the descriptor status
entry unless both BUFF and
OFLO errors occur at the same
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