參數(shù)資料
型號(hào)： AM79C965KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 40/220頁(yè)
文件大?。?/td> 1197K
代理商： AM79C965KCW
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AMD
P R E L I M I N A R Y
134
Am79C965
which the PCnet-32 controller
will store incoming frame data.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
H_RESET,
S_RESET, or STOP.
CSR19: Current Receive Buffer Address Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CRBA
Contains the upper 16 bits of the
current receive buffer address at
which the PCnet-32 controller
will store incoming frame data.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
H_RESET,
S_RESET, or STOP.
CSR20: Current Transmit Buffer Address Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CXBA
Contains the lower 16 bits of the
current transmit buffer address
from which the PCnet-32 control-
ler is transmitting.
Read/write accessible only when
STOP bit is set.
CSR21: Current Transmit Buffer Address Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CXBA
Contains the upper 16 bits of the
current transmit buffer address
from which the PCnet-32 control-
ler is transmitting.
Read/write accessible only when
STOP bit is set.
CSR22: Next Receive Buffer Address Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRBA
Contains the lower 16 bits of the
next receive buffer address to
which the PCnet-32 controller
will store incoming frame data.
Read/write accessible only when
STOP bit is set.
CSR23: Next Receive Buffer Address Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRBA
Contains the upper 16 bits of the
next receive buffer address to
which the PCnet-32 controller
will store incoming frame data.
Read/write accessible only when
STOP bit is set.
CSR24: Base Address of Receive Ring Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BADR
Contains the lower 16 bits of the
base address of the Receive
Ring.
Read/write accessible only when
STOP bit is set.
CSR25: Base Address of Receive Ring Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BADR
Contains the upper 16 bits of the
base address of the Receive
Ring.
Read/write accessible only when
STOP bit is set.
CSR26: Next Receive Descriptor Address Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRDA
Contains the lower 16 bits of the
next RDRE address pointer.
Read/write accessible only when
STOP bit is set.
CSR27: Next Receive Descriptor Address Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
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