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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 27/220頁 |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
122
Am79C965
USER ACCESSIBLE REGISTERS
The PCnet-32 controller implements all PCnet-ISA
(Am79C960) registers, all LANCE (Am7990) registers,
all ILACC (Am79C900) registers, plus a number of addi-
tional registers. The PCnet-32 controller registers are
compatible with both the PCnet-ISA (Am79C960) regis-
ters and all of the LANCE (Am7990) registers upon
power up. Compatibility to the ILACC set of registers
requires one access to the Software Style register
(BCR20, bits 7–0) to be performed. By setting an appro-
priate value of the Software Style register (BCR20, bits
7–0) the user can select a set of registers that are com-
patible with the ILACC set of registers.
Note that all register locations are defined to be 16 bits in
width when WIO mode is selected. When DWIO mode is
selected, all register locations are defined to be 32 bits in
width. When performing register write operations in
DWIO mode, the upper 16 bits should always be written
as zeros, except APROM locations. When performing
register read operations in DWIO mode, the upper 16
bits of I/O resources should always be written as ZE-
ROs, except for APROM locations and CSR88. When
performing register read operations in DWIO mode, the
upper 16 bits of I/O resources should always be re-
garded as having undefined values, except for the
APROM locations and CSR88.
PCnet-32 controller registers can be divided into three
groups:
Setup registers:
Registers that are intended to
be initialized by the system
initialization
procedure
(e.g.
BIOS device initialization rou-
tine) or by the device driver to
program the operation of vari-
ous
PCnet-32
controller
features
Running registers:
Registers that are intended to
be used by the device driver
software once the PCnet-32
controller is running to access
status information and to pass
control information
Test registers:
Registers that are intended to
be used only for testing and di-
agnostic purposes
Below is a list of the registers that fall into each of the first
two categories. Those registers that are not included in
either of these lists can be assumed to be intended for
diagnostic purposes.
Setup Registers
The following is a list of those registers that would typi-
cally need to be programmed once during the setup of
the PCnet-32 controller within a system. The control bits
in each of these registers typically do not need to be
modified once they have been written. However, there
are no restrictions as to how many times these registers
may actually be accessed. Note that if the default power
up values of any of these registers is acceptable to the
application, then such registers need never be ac-
cessed at all. Also note that some of these registers may
be programmable through the EEPROM read opera-
tion, and therefore do not necessarily need to be written
to by the system initialization procedure or by the driver
software.
CRS1
Initialization Address[15:0]
CSR2
Initialization Address[31:16]
CSR3
Interrupt Masks and Deferral Control
CSR4
Test and Features Control
CSR8
Logical Address Filter [15:0]
CSR9
Logical Address Filter [31:16]
CSR10
Logical Address Filter [47:32]
CSR11
Logical Address Filter [63:48]
CSR12
Physical Address Filter [15:0]
CSR13
Physical Address Filter [31:16]
CSR14
Physical Address Filter [47:32]
CSR15
Mode Register
CSR24
Base Address of Receive Ring Lower
CSR25
Base Address of Receive Ring Upper
CSR30
Base Address of Transmit Ring Lower
CRS31
Base Address of Transmit Ring Upper
CSR47
Polling Interval
CSR58
Software Style
CSR76
Receive Ring Length
CSR78
Transmit Ring Length
CSR80
Cycle Register and FIFO
Threshold Control
CSR82
Bus Activity Timer
CSR100
Memory Error Time-out Register
CSR122
Receiver Packet Alignment Control
BCR2
MAU configuration
BCR16
I/O Base Address Lower
BCR17
I/O Base Address Upper
BCR18
Bus Size and Burst Control Register
BCR19
EEPROM Control and Status Register
BCR20
Software Style
BCR21
Interrupt Control
Running Registers
The following is a list of those registers that would typi-
cally need to be periodically read and perhaps written
during the normal running operation of the PCnet-32
controller within a system. Each of these registers con-
tains control bits or status bits or both.
RAP
Register Address Port Register
CSR0
PCnet-32 Controller Status Register
CSR4
Test and Features Control
CSR112
Missed Frame Count
CSR114
Receive Collision Count
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