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參數資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數： | 3/220頁 |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
100
Am79C965
There are four possible operation modes in the
BSR cell:
1
Capture
2
Shift
3
Update
4
System Function
Other Data Register
1) BYPASS REG (1 Bit)
2) DEV ID REG (32 bits)
Bits 31–28:
Version
Bits 27–12:
Part number (0010 0100 0011 0000)
Bits 11–1:
Manufacturer ID. The 11 bit
manufacturer ID code for AMD is
00000000001 according to JEDEC
Publication 106-A.
Bit 0:
Always a logic 1
3) INSCAN0
This is an internal scan path for AMD internal test-
ing use.
EADI (External Address Detection
Interface)
This interface is provided to allow external address filter-
ing. It is selected by setting the EADISEL bit in BCR2 to
a ONE. This feature is typically utilized for terminal serv-
ers, bridges and/or router products. The EADI interface
can be used in conjunction with external logic to capture
the packet destination address from the serial bit stream
as it arrives at the PCnet-32 controller, compare the
captured address with a table of stored addresses or
identifiers, and then determine whether or not the
PCnet-32 controller should accept the packet.
The EADI interface outputs are delivered directly from
the NRZ decoded data and clock recovered by the
Manchester decoder or input into the GPSI port. This
allows the external address detection to be performed in
parallel with frame reception and address comparison in
the MAC Station Address Detection (SAD) block of the
PCnet-32 controller.
SRDCLK is provided to allow clocking of the receive bit
stream into the external address detection logic.
SRDCLK runs only during frame reception activity.
Once a received frame commences and data and clock
are available from the decoder, the EADI logic will moni-
tor the alternating (“1,0”) preamble pattern until the two
ones of the Start Frame Delimiter (“1,0,1,0,1,0,1,1”) are
detected, at which point the SF/BD output will be
driven HIGH.
The SF/BD signal will initially be LOW. The assertion of
SF/BD is a signal to the external address detection logic
that the SFD has been detected and that subsequent
SRDCLK cycles will deliver packet data to the external
logic. Therefore, when SF/BD is asserted, the external
address matching logic should begin de-serialization of
the SRD data and send the resulting destination ad-
dress to a content addressable memory (CAM) or other
address detection device.
In order to reduce the amount of logic external to the
PCnet-32 controller for multiple address decoding sys-
tems, the SF/BD signal will toggle at each new byte
boundary within the packet, subsequent to the SFD.
This eliminates the need for externally supplying byte
framing logic.
The
EAR pin should be driven LOW by the external ad-
dress comparison logic to reject a frame.
If an address match is detected by internal address
comparison with either the Physical or Logical or broad-
cast Address contained within the PCnet-32 controller,
then the frame will be accepted regardless of the condi-
tion of
EAR. Internal address match is disabled when
PROM (CSR15[15]) = 0, DRCVBC (CSR15[14]) = 1,
DRCVPA (CSR15[13]) = 1 and Logical Address Filter
(CSR8–CSR11) = 0.
When the EADISEL bit of BCR2 is set to a ONE and
internal address match is disabled, then all incoming
frames will be accepted by the PCnet-32 controller, un-
less the
EAR pin becomes active during the first 64
bytes of the frame (excluding preamble and SFD). This
allows external address lookup logic approximately 58
byte times after the last destination address bit is avail-
able to generate the
EAR signal, assuming that the
PCnet-32 controller is not configured to accept runt
packets.
EAR will be ignored after 64 byte times after the
SFD. The frame will be accepted if
EAR has not been
asserted before this time. If Runt Packet Accept is en-
abled, then the
EAR signal must be generated prior to
the receive message completion, if packet rejection is to
be guaranteed. Runt packet sizes could be as short as
12 byte times (assuming 6 bytes for source address,
2 bytes for length, no data, 4 bytes for FCS) after the last
bit of the destination address is available.
EAR must
have a pulse width of at least 150 ns.
When the EADISEL bit of BCR2 is set to a ONE and the
PROM bit of the Mode Register is set to a ONE, then all
incoming frames will be accepted by the PCnet-32 con-
troller, regardless of any activity on the
EAR pin.
The EADI outputs continue to provide data throughout
the reception of a packet. This allows the external logic
to capture packet header information to determine
protocol type, inter-networking information, and other
useful data.
The EADI interface will operate as long as the STRT bit
in CSR0 is set, even if the receiver and/or transmitter
are disabled by software (DTX and DRX bits in CSR15
are set). This configuration is useful as a semi-power-
down mode in that the PCnet-32 controller will not per-
form any power-consuming DMA operations. However,
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相關代理商/技術參數 |
參數描述 |
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| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
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| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
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