參數(shù)資料
型號(hào)： AM79C965KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁數(shù)： 72/220頁
文件大?。?/td> 1197K
代理商： AM79C965KCW
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P R E L I M I N A R Y
AMD
163
Am79C965
BCR19: EEPROM Control and Status
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
PVALID
EEPROM Valid status bit. This
bit is read only by the host. A
value of ONE in this bit indicates
that a PREAD operation has oc-
curred, and that 1) there is an
EEPROM
connected
to
the
PCnet-32 controller microwire in-
terface pins and 2) the contents
read from the EEPROM have
passed the checksum verifica-
tion operation.
A value of ZERO in this bit indi-
cates that the contents of the
EEPROM are different from the
contents
of
the
applicable
PCnet-32
controller
on-board
registers and/or that the check-
sum for the entire 36 bytes of
EEPROM is incorrect or that no
EEPROM is connected to the
microwire interface pins.
PVALID is set to ZERO during
H_RESET and is unaffected by
S_RESET or the STOP bit. How-
ever, following the H_RESET op-
eration, an automatic read of the
EEPROM will be performed. Just
as is true for the normal PREAD
command, at the end of this auto-
matic
read
operation,
the
PVALID bit may be set to ONE.
Therefore, H_RESET will set the
PVALID bit to ZERO at first, but
the automatic EEPROM read op-
eration may later set PVALID to a
ONE.
If PVALID becomes ZERO fol-
lowing an EEPROM read opera-
tion
(either
automatically
generated after H_RESET, or re-
quested through PREAD), then
all
EEPROM-programmable
BCR locations will be reset to
their H_RESET values.
If no EEPROM is present at the
EESK, EEDI and EEDO pins,
then all attempted PREAD com-
mands will terminate early and
PVALID will NOT be set. This ap-
plies to the automatic read of the
EEPROM after H_RESET as
well as to host-initiated PREAD
commands.
14
PREAD
EEPROM Read command bit.
When this bit is set to a ONE by
the
host,
the
PVALID
bit
(BCR19[15]) will immediately be
reset to a ZERO and then the
PCnet-32 controller will perform
a read operation of 36 bytes from
the
EEPROM
through
the
microwire
interface.
The
EEPROM data that is fetched
during the read will be stored in
the appropriate internal registers
on board the PCnet-32 control-
ler. Upon completion of the
EEPROM read operation, the
PCnet-32 controller will assert
the PVALID bit. EEPROM con-
tents will be indirectly accessible
to the host through I/O read ac-
cesses to the Address PROM
(offsets 0h through Fh) and
through I/O read accesses to
other EEPROM programmable
registers. Note that I/O read ac-
cesses from these locations will
not actually access the EEPROM
itself, but instead will access the
PCnet-32
controller’s
internal
copy of the EEPROM contents.
I/O write accesses to these loca-
tions may change the PCnet-32
controller register contents, but
the EEPROM locations will not
be affected. EEPROM locations
may
be
accessed
directly
through BCR19.
At the end of the read operation,
the PREAD bit will automatically
be reset to a ZERO by the
PCnet-32 controller and PVALID
will bet set, provided that an
EEPROM
existed
on
the
microwire interface pins and that
the checksum for the entire 36
bytes of EEPROM was correct.
Note that when PREAD is set to a
ONE, then the PCnet-32 control-
ler will no longer respond to I/O
accesses directed toward it, until
the PREAD operation has com-
pleted successfully.
If a PREAD command is given to
the PCnet-32 controller but no
EEPROM is attached to the
microwire interface pins, then the
PREAD command will terminate
early, the PREAD bit will be
cleared to a ZERO and the
PVALID bit will remain reset with
a value of ZERO. The PCnet-32
controller will then enter Soft-
ware Relocatable Mode to await
further programming. This ap-
plies to the automatic read of the
EEPROM after H_RESET as
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