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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 206/220頁 |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
86
Am79C965
Buffer Management Unit
The buffer management unit is a micro-coded state
machine which implements the initialization procedure
and manages the descriptors and buffers. The buffer
management unit operates at a speed of BCLK
÷2.
Initialization
PCnet-32 controller initialization includes the reading of
the initialization block in memory to obtain the operating
parameters. The initialization block must be located on a
double word (4-byte) address boundary, regardless of
the setting of the SSIZE32, (CSR58[8]/BCR20[8]) bit.
The initialization block is read when the INIT bit in CSR0
is set. The INIT bit should be set before or concurrent
with the STRT bit to insure correct operation. Two
doublewords are read during each period of bus master-
ship. When SSIZE32 = 1 (CSR58[8]/ BCR20[8]) , this
results in a total of 4 arbitration cycles (3 arbitration cy-
cles if SSIZE32 = 0). Once the initialization block has
been completely read in and internal registers have
been updated, IDON will be set in CSR0, and an inter-
rupt generated (if IENA is set). At this point, the BMU
knows where the receive and transmit descriptor rings
and hence, normal network operations will begin.
The Initialization Block is vectored by the contents of
CSR1 (least significant 16 bits of address) and CSR2
(most significant 16 bits of address). The block contains
the user defined conditions for PCnet-32 controller op-
eration, together with the base addresses and length
information of the transmit and receive descriptor rings.
There is an alternative method to initialize the PCnet-32
controller. Instead of initialization via the initialization
block in memory, data can be written directly into the
appropriate registers. Either method may be used at the
discretion of the programmer. If the registers are written
to directly, the INIT bit must not be set, or the initializa-
tion block will be read in, thus overwriting the previously
written information. Please refer to Appendix C for de-
tails on this alternative method.
Re-Initialization
The transmitter and receiver sections of the PCnet-32
controller can be turned on via the initialization block
(MODE Register DTX, DRX bits; CSR15[1:0]). The
states of the transmitter and receiver are monitored by
the host through CSR0 (RXON, TXON bits). The
PCnet-32 controller should be reinitialized if the trans-
mitter and/or the receiver were not turned on during the
original initialization, and it was subsequently required
to activate them or if either section was shut off due to
the detection of an error condition (MER, UFLO, TX
BUFF error).
Re-initialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing
to CSR15, and then setting the START bit in CSR0.
Note that this form of restart will not perform the same in
the PCnet-32 controller as in the LANCE. In particular,
upon restart, the PCnet-32 controller reloads the
transmit and receive descriptor pointers with their
respective base addresses. This means that the soft-
ware must clear the descriptor own bits and reset its
descriptor ring pointers before the restart of the
PCnet-32 controller. The reload of descriptor base ad-
dresses is performed in the LANCE only after initializa-
tion, so a restart of the LANCE without initialization
leaves the LANCE pointing at the same descriptor loca-
tions as before the restart.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in mem-
ory. There are two rings, a receive ring and a transmit
ring. The size of a message descriptor entry is 4
doublewords, or 16 bytes, when SSIZE32 = 1. The size
of a message descriptor entry is 4 words, or 8 bytes,
when SSIZE32 = 0 (CSR58[8]/BCR20[8]).
Descriptor Rings
Each descriptor ring must be organized in a contiguous
area of memory. At initialization time (setting the INIT bit
in CSR0), the PCnet-32 controller reads the user-de-
fined base address for the transmit and receive descrip-
tor rings, as well as the number of entries contained in
the descriptor rings. Descriptor ring base addresses
must be on a 16-byte boundary when SSIZE32 = 1, or on
an 8-byte boundary when SSIZE32 = 0. A maximum of
128 (or 512, depending upon the value of SSIZE32) ring
entries is allowed when the ring length is set through the
TLEN and RLEN fields of the initialization block. How-
ever, the ring lengths can be set beyond this range (up to
65535) by writing the transmit and receive ring length
registers (CSR76, CSR78) directly.
Each ring entry contains the following information:
1. The address of the actual message data buffer in
user or host memory
2. The length of the message buffer
3. Status information indicating the condition of the
buffer
To permit the queuing and de-queuing of message buff-
ers, ownership of each buffer is allocated to either the
PCnet-32 controller or the host. The OWN bit within the
descriptor status information, either TMD or RMD (see
section on TMD or RMD), is used for this purpose.
OWN = “1” signifies that the PCnet-32 controller cur-
rently has ownership of this ring descriptor and its asso-
ciated buffer. Only the owner is permitted to relinquish
ownership or to write to any field in the descriptor entry.
A device that is not the current owner of a descriptor
entry cannot assume ownership or change any field in
the entry. A device may, however, read from a descrip-
tor that it does not currently own. Software should al-
ways read descriptor entries in sequential order. When
software finds that the current descriptor is owned by the
PCnet-32 controller, then the software must not read
“ahead” to the next descriptor. The software should wait
at the unOWNed descriptor until ownership has been
granted to the software (when SPRINTEN = 1 (CSR3,
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