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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 217/220頁 |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
96
Am79C965
PLL Tracking
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
rection circuit. This circuit ensures that the phase-
locked clock remains locked on the received signal.
Individual bit cell phase corrections of the Voltage
Controlled Oscillator (VCO) are limited to 10% of the
phase difference between BCC and phase-locked
clock. Hence, input data jitter is reduced in ISRDCLK by
10 to 1.
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI
± inputs after
IRXCRS is asserted for an end of message. IRXCRS
de-asserts 1 to 2 bit times after the last positive transi-
tion on the incoming message. This initiates the end of
reception cycle. The time delay from the last rising edge
of the message to IRXCRS de-assert allows the last bit
to be strobed by ISRDCLK and transferred to the con-
troller section, but prevents any extra bit(s) at the end
of message.
Data Decoding
The data receiver is a comparator with clocked output to
minimize noise sensitivity to the DI
±/RXD± inputs. Input
error is less than
± 35 mV to minimize sensitivity to input
rise and fall time. ISRDCLK strobes the data receiver
output at 1/4 bit time to determine the value of the
Manchester bit, and clocks the data out on IRXDAT on
the following ISRDCLK. The data receiver also gener-
ates the signal used for phase detector comparison to
the internal MENDEC voltage controlled oscillator
(VCO).
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with the
values 1010b. Clock is phase-locked to the negative
transition at the bit cell center of the second “0” in
the pattern.
Since data is strobed at 1/4 bit time, Manchester transi-
tions which shift from their nominal placement through
1/4 bit time will result in improperly decoded data. With
this as the criteria for an error, a definition of “Jitter
Handling” is:
The peak deviation approaching or crossing 1/4 bit
cell position from nominal input transition, for which
the MENDEC section will properly decode data.
Attachment Unit Interface(AUI)
The AUI is the PLS (Physical Layer Signaling) to PMA
(Physical Medium Attachment) interface which effec-
tively connects the DTE to a MAU. The differential
interface provided by the PCnet-32 controller is fully
compliant to Section 7 of ISO 8802-3 (ANSI/IEEE
802.3).
After the PCnet-32 controller initiates a transmission it
will expect to see data “l(fā)ooped-back” on the DI
± pair
(when the AUI port is selected). This will internally gen-
erate a “carrier sense”, indicating that the integrity of the
data path to and from the MAU is intact, and that the
MAU is operating correctly. This “carrier sense” signal
must be asserted within TBD bit times after the first
transmitted bit on DO
± (when using the AUI port). If “car-
rier sense” does not become active in response to the
data transmission, or becomes inactive before the end
of transmission, the loss of carrier (LCAR) error bit will
be set in the Transmit Descriptor Ring (TMD2, bit27)
after the frame has been transmitted.
Differential Input Terminations
The differential input for the Manchester data (DI
±) is
externally terminated by two 40.2
±1% resistors and
one optional common-mode bypass capacitor, as
shown in the Differential Input Termination diagram be-
low. The differential input impedance, ZIDF, and the
common-mode input impedance, ZICM, are specified so
that the Ethernet specification for cable termination im-
pedance is met using standard 1% resistor terminators.
If SIP devices are used, 39
is also a suitable value.
The CI
± differential inputs are terminated in exactly the
same way as the DI
± pair.
PCnet-ISA
DI+
DI-
40.2
40.2
0.01
F
to 0.1
F
AUI Isolation
Transformer
16907B-9
18219B-38
PCnet-32
Figure 31. AUI Differential Input Termination
Collision Detection
A MAU detects the collision condition on the network
and generates a differential signal at the CI
± inputs. This
collision signal passes through an input stage which de-
tects signal levels and pulse duration. When the signal is
detected by the MENDEC it sets the ICLSN line HIGH.
The condition continues for approximately 1.5 bit times
after the last LOW-to-HIGH transition on CI
±.
Twisted-Pair Transceiver (T-MAU)
The T-MAU implements the Medium Attachment Unit
(MAU) functions for the Twisted Pair Medium, as speci-
fied by the supplement to ISO 8802-3 (IEEE/ANSI
802.3) standard (Type 10BASE-T). The T-MAU pro-
vides twisted pair driver and receiver circuits, including
on-board transmit digital predistortion and receiver
squelch and a number of additional features including
Link Status indication, Automatic Twisted Pair Receive
Polarity Detection/Correction and Indication, Receive
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