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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 154/220頁 |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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P R E L I M I N A R Y
AMD
39
Am79C965
Table 14. CLL Value and Floating Address Pins
Floated Portion of Address
Bus During AHOLD
00000
None
00001
A31–A2
00010
A31–A3
00011
Reserved CLL Value
00100
A31–A4
00101–00111
Reserved CLL Values
01000
A31–A5
01001–01111
Reserved CLL Values
10000
A31–A6
10001–11111
Reserved CLL Values
CLL Value
BCLK
Bus Clock
Input
Clock input that provides timing edges for all interface
signals. This clock is used to drive the system bus inter-
face and the internal buffer management unit. This clock
is NOT used to drive the network functions.
BE0–BE3
Byte Enable
Input/Output
These signals indicate which bytes on the data bus are
active during read and write cycles. When
BE3 is active,
the byte on D31–D24 is valid.
BE2–BE0 active indicate
valid data on pins D23–D16, D15–D8, D7–D0, respec-
tively. The byte enable signals are outputs for bus mas-
ter and inputs for bus slave operations.
BLAST
Burst Last
Output
When the
BLAST signal is asserted, then the next time
that
BRDY or RDYRTN is asserted, the burst cycle
is complete.
BOFF
Backoff
Input
BOFF is monitored as an input during Bus Master ac-
cesses. When PCnet-32 controller is current local bus
master, it will float all appropriate bus mastering signals
within 1 clock period of the assertion of
BOFF. When
BOFF is deasserted, PCnet-32 controller will restart any
accesses that were suspended due to the assertion of
BOFF and then will proceed with other scheduled ac-
cesses, if any. Register access cannot be performed to
the PCnet-32 device while
BOFF is asserted.
BRDY
Burst Ready
Input/Output
BRDY functions as an input to the PCnet-32 controller
during bus master cycles. When
BRDY is asserted dur-
ing a master cycle, it indicates to the PCnet-32 controller
that the target device is accepting burst transfers. It also
serves the same function as
RDYRTN does for non-
burst accesses. That is, it indicates that the target de-
vice has accepted the data on a master write cycle, or
that the target device has presented valid data onto the
bus during master read cycles.
If
BRDY and RDYRTN are sampled active in the same
cycle, then
RDYRTN takes precedence, causing the
next transfer cycle to begin with a T1 cycle.
BRDY functions as an output during PCnet-32 controller
slave cycles and is always driven inactive (HIGH).
BRDY is floated if the PCnet-32 controller is not being
accessed as the current slave device on the local bus.
D/C
Data/Control Select
Input/Output
During slave accesses to the PCnet-32 controller, the
D/
C pin, along with M/IO and W/R, indicates the type of
cycle that is being performed. PCnet-32 controller will
only respond to local bus accesses in which D/
C is
driven HIGH by the local bus master.
During PCnet-32 controller bus master accesses, the
D/
C pin is an output and will always be driven HIGH.
D/
C is floated if the PCnet-32 controller is not the current
master on the local bus.
D0–D31
Data Bus
Input/Output
Used to transfer data to and from the PCnet-32 control-
ler to system resources via the local bus. D31–D0 are
driven by the PCnet-32 controller when performing bus
master writes and slave read operations. Data on
D31–D0 is latched by the PCnet-32 controller when
performing
bus
master
reads
and
slave
write
operations.
The PCnet-32 controller will always follow Am386DX
byte lane conventions. This means that for word and
byte accesses in which PCnet-32 controller drives the
data bus (i.e. master write operations and slave read
operations) the PCnet-32 controller will produce dupli-
cates of the active bytes on the unused half of the 32-bit
data bus. Table 15 illustrates the cases in which dupli-
cate bytes are created.
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