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| 型號(hào)： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 20/220頁(yè) |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
116
Am79C965
SHFBUSY will be HIGH for the entire EEPROM read
operation, and therefore all EEPROM contents will have
been shifted through the external logic before it settles
on its final, programmed value. If the EEPROM check-
sum verification fails, then the EEPROM contents are
assumed to be invalid, and the SHFBUSY signal will re-
main HIGH after the completion of the EEPROM read
operation. This action will prevent incorrect system logic
values from being driven into the system. If the
EEPROM checksum verification passes, then the
EEPROM contents are assumed to be valid, and the
SHFBUSY signal will return to a LOW state after the
completion of the EEPROM read operation.
Transmit Operation
The transmit operation and features of the PCnet-32
controller are controlled by programmable options.
Transmit Function Programming
Automatic transmit features such as retry on collision,
FCS generation/transmission, and pad field insertion
can all be programmed to provide flexibility in the
(re-)transmission of messages.
Disable retry on collision (DRTY) is controlled by the
DRTY bit of the Mode register (CSR15) in the initializa-
tion block.
Automatic pad field insertion is controlled by the
APAD_XMT bit in CSR4. If APAD_XMT is set, auto-
matic pad field insertion is enabled, the DXMTFCS fea-
ture is over-ridden, and the 4 byte FCS will be added to
the transmitted frame unconditionally. If APAD_XMT is
clear, no pad field insertion will take place and runt pack-
et transmission is possible.
The disable FCS generation/transmission feature can
be programmed dynamically on a frame by frame basis.
See the ADD_FCS description of TMD1.
Transmit FIFO Watermark (XMTFW in CSR80) sets the
point at which the BMU requests more data from the
transmit buffers for the FIFO. A minimum of “XMTFW”
empty spaces must be available in the transmit FIFO
before the BMU will request the system bus in order to
transfer transmit packet data into the transmit FIFO.
Transmit Start Point (XMTSP in CSR80) sets the point
when the transmitter actually attempts to transmit a
frame onto the media. A minimum of “XMTSP” bytes
must be written to the transmit FIFO for the current
frame before transmission of the current frame will be-
gin. (When automatically padded packets are being
sent, it is conceivable that the XMTSP is not reached
when all of the data has been transferred to the FIFO. In
this case, the transmission will begin when all of the
packet data has been placed into the transmit FIFO.)
When the entire frame is in the FIFO, attempts at trans-
mission of preamble will commence regardless of the
value in XMTSP. The default value of XMTSP is 10b,
meaning 64 bytes full.
Automatic Pad Generation
Transmit frames can be automatically padded to extend
them to 64 data bytes (excluding preamble). This allows
the minimum frame size of 64 bytes (512 bits) for
802.3/Ethernet to be guaranteed with no software inter-
vention from the host/controlling process. Setting the
APAD_XMT bit in CSR4 enables the automatic padding
feature. The pad is placed between the LLC data field
and FCS field in the 802.3 frame (see Figure 35). FCS is
always added if the frame is padded, regardless of the
state of DXMTFCS. The transmit frame will be padded
by bytes with the value of 00h. The default value of
APAD_XMT is 0; this will disable auto pad generation
after H_RESET.
It is the responsibility of upper layer software to correctly
define the actual length field contained in the message
to correspond to the total number of LLC Data bytes en-
capsulated in the packet (length field as defined in the
ISO 8802-3 (IEEE/ANSI 802.3) standard). The length
value contained in the message is not used by the
PCnet-32 controller to compute the actual number of
pad bytes to be inserted. The PCnet-32 controller will
append pad bytes dependent on the actual number of
bits transmitted onto the network. Once the last data
byte of the frame has completed, prior to appending the
FCS, the PCnet-32 controller will check to ensure that
544 bits have been transmitted. If not, pad bytes are
added to extend the frame size to this value, and the
FCS is then added.
Preamble
1010....1010
Sync
10101011
Destination
Address
Source
Address
Length
LLC
Data
Pad
FCS
4
Bytes
46 — 1500
Bytes
2
Bytes
6
Bytes
6
Bytes
8
Bits
56
Bits
18219B-42
Figure 35. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
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| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
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