參數(shù)資料
型號： AM79C965KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁數(shù)： 49/220頁
文件大小： 1197K
代理商： AM79C965KCW
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AMD
P R E L I M I N A R Y
142
Am79C965
binary number used to number
the current receive descriptor.
This counter interprets the value
in CSR76 as pointing to the first
descriptor. a counter value of
zero corresponds to the last de-
scriptor in the ring.
Read/write accessible only when
STOP bit is set.
CSR74: Transmit Ring Counter
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
XMTRC
Transmit Ring Counter location.
Contains a Two’s complement
binary number used to number
the current transmit descriptor.
This counter interprets the value
in CSR78 as pointing to the first
descriptor. A counter value of
zero corresponds to the last de-
scriptor in the ring.
Read/write accessible only when
STOP bit is set.
CSR76: Receive Ring Length
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RCVRL
Receive Ring Length. Contains
the two’s complement of the re-
ceive descriptor ring length. This
register is initialized during the
PCnet-32 controller initialization
routine based on the value in the
RLEN field of the initialization
block. However, this register can
be manually altered. the actual
receive ring length is defined by
the current value in this register.
The ring length can be defined as
any value from 1 to 65535.
Read/write accessible only when
STOP bit is set.
CSR78: Transmit Ring Length
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
XMTRL
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the PCnet-32 controller initializa-
tion routine based on the value in
the TLEN field of the initialization
block. However, this register can
be manually altered. the actual
transmit ring length is defined by
the current value in this register.
The ring length can be defined as
any value from 1 to 65535.
Read/write accessible only when
STOP bit is set.
CSR80: Burst and FIFO Threshold Control
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-14
RES
Reserved locations. Read as
ones and written as zero.
13-12 RCVFW[1:0]
Receive
FIFO
Watermark.
RCVFW controls the point at
which receive DMA is requested
in relation to the number of re-
ceived bytes in the receive FIFO.
RCVFW specifies the number of
bytes which must be present
(once the frame has been veri-
fied as a non-runt) before receive
DMA is requested. Note however
that in order for receive DMA to
be performed for a new frame, at
least 64 bytes must have been
received. This effectively avoids
having to react to receive frames
which are runts or suffer a colli-
sion during the slot time (512 bit
times). If the Runt Packet Accept
feature is enabled, receive DMA
will be requested as soon as
either the RCVFW threshold is
reached, or a complete valid
receive frame is detected (re-
gardless of length). RCVFW is
set to a value of 10 (64 bytes) af-
ter H_RESET or S_RESET and
is unaffected by STOP.
RCVFW[1:0]
Bytes Received
00
16
01
32
10
64
11
Reserved
Read/write accessible only when
STOP bit is set.
Certain combinations of water-
mark programming and LINBC
(BCR18[2-0]) programming may
create situations where no linear
bursting is possible, or where the
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