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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 50/220頁 |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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P R E L I M I N A R Y
AMD
143
Am79C965
FIFO may be excessively read or
excessively written. Such combi-
nations are declared as illegal.
Combinations of watermark set-
tings and LINBC settings must
obey the following relationship:
watermark (in bytes)
≥ LINBC (in
bytes)
Combinations of watermark and
LINBC settings that violate this
rule may cause unexpected be-
havior.
11-10 XMTSP[1:0]
Transmit Start Point. XMTSP
controls the point at which pre-
amble
transmission
attempts
commence in relation to the num-
ber of bytes written to the trans-
mit FIFO for the current transmit
frame. When the entire frame is
in the FIFO, transmission will
start regardless of the value in
XMTSP. XMTSP is given a value
of 10 (64 bytes) after H_RESET
or S_RESET and is unaffected
by
STOP.
Regardless
of
XMTSP, the FIFO will not inter-
nally over write its data until at
least 64 bytes (or the entire frame
if <64 bytes) have been transmit-
ted onto the network. This en-
sures that for collisions within the
slot time window, transmit data
need not be re-written to the
transmit FIFO, and re-tries will be
handled autonomously by the
MAC. This bit is read/write ac-
cessible only when the STOP bit
is set.
XMTSP[1:0]
Bytes Written
00
4
01
16
10
64
11
112
9-8 XMTFW[1:0]
Transmit
FIFO
Watermark.
XMTFW specifies the point at
which
transmit
DMA
stops,
based upon the number of write
cycles that could be performed to
the transmit FIFO without FIFO
overflow. Transmit DMA is al-
lowed at any time when the num-
ber of write cycles specified by
SMTFW could be executed with-
out causing transmit FIFO over-
flow. XMTFW is set to a value of
00b (8 cycles) after H_RESET or
S_RESET and is unaffected by
STOP. Read/write accessible
only when STOP bit is set.
XMTFW[1:0]
Write Cycles
00
8
01
16
10
32
11
Reserved
Certain combinations of water-
mark programming and LINBC
programming may create situ-
ations where no linear bursting is
possible, or where the FIFO may
be excessively read or exces-
sively written. Such combina-
tions are declared as illegal.
Combinations of watermark set-
tings and LINBC settings must
obey the following relationship:
watermark (in bytes)
≥ LINBC (in
bytes)
Combinations of watermark and
LINBC settings that violate this
rule may cause unexpected be-
havior.
7-0 DMACR[7:0]
DMA Cycle Register. This regis-
ter contains the maximum allow-
able number of transfers to
system memory that the Bus In-
terface will perform during a
single DMA cycle. The Cycle
Register is not used to limit the
number of transfers during De-
scriptor transfers. A value of zero
will be interpreted as one trans-
fer. During H_RESET or S_RE-
SET a value of 16 is loaded in the
BURST
register.
If
the
DMAPLUS bit in CSR4 is set, the
DMA Cycle Register is disabled.
When the ENTST bit in CSR4 is
set, all writes to this register will
automatically perform a decre-
ment cycle.
When the Cycle Register times
out in the middle of a linear burst,
the linear burst will continue until
a
legal
starting
address
is
reached, and then the PCnet-32
controller will relinquish the bus.
Therefore, if linear bursting is en-
abled, and the user wishes the
PCnet-32 controller to limit bus
activity to desired_max transfers,
then the Cycle Register should
be programmed to a value of:
Burst
count
setting
=
(de-
sired_max DIV (length of linear
burst in transfers)) x length of lin-
ear burst in transfers where DIV
is the operation that yields the
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