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參數(shù)資料
| 型號(hào)： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 153/220頁(yè) |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
38
Am79C965
Table 13. Pin Connections to Power/Ground
Resistive
Supply
Connection
Recommended
Pin Name
Pin No
Strapping
to Supply
Resistor Size
LED2/SRDCLK
2
Required
324
in series with LED, or 10 K
without LED
AHOLD
25
Optional
Required
10 K
Am486
31
Required
Optional
NA
BOFF
54
Optional
Required
10 K
HOLDI/TDO
100
Optional
Required
10 K
JTAGSEL
106
Required
Optional
NA
EEDO/LEDPRE3/SRD
152
Optional
Required
10 K
LB/
VESA
153
Required
Optional
NA
EEDI/
LNKST
154
Optional
Required
324
in series with LED, or 10 K
without LED
EESK/LED1/SFBD
155
Required
324
in series with LED, or 10 K
without LED
SLEEP
156
Optional
Required
10 K
All Other Pins
—
Optional
Required
10 K
Pin Connections to VDD or VSS
Several pins may be connected to VDD or VSS for various
application options. Some pins are required to be con-
nected to VDD or VSS in order to set the controller into a
particular mode of operation, while other pins might be
connected to VDD or VSS if that pin’s function is not imple-
mented in a specific application. Table 13 shows which
pins
require a connection to VDD or VSS, and which pins
may
optionally be connected to VDD or VSS because the
application does not support that pin’s function. The
table also shows whether or not the connections need to
be resistive.
Local Bus Interface
A2–A31
Address Bus
Input/Output
Address information which is stable during a bus opera-
tion, regardless of the source. When the PCnet-32 con-
troller is Current Master, A1–A31 will be driven. When
the PCnet-32 controller is not Current Master, the
A2–A31 lines are continuously monitored to determine if
an address match exists for I/O slave transfers.
Some portion of the Address Bus will be floated at the
time of an address hold operation, which is signaled with
the AHOLD pin. The number of Address Bus pins to be
floated will be determined by the value of the Cache Line
Length register (BCR18, bits 15-11).
ADS
Address Status
Input/Output
When driven LOW, this signal indicates that a valid bus
cycle definition and address are available on the M/
IO,
D/
C, W/R and A2–A31 pins of the local bus interface. At
that time, the PCnet-32 controller will examine the com-
bination of M/
IO, D/C, W/R, and the A2–A31 pins to
determine if the current access is directed toward the
PCnet-32 controller.
ADS will be driven LOW when the PCnet-32 controller
performs a bus master access on the local bus.
AHOLD
Address Hold
Input
This pin is always an input. The PCnet-32 controller will
put some portion of the address bus into a high imped-
ance state whenever this signal is asserted. AHOLD
may be asserted by an external cache controller when a
cache invalidation cycle is being performed. AHOLD
may be asserted at any time, including times when the
PCnet-32 controller is the active bus master. Note that
this pin is multiplexed with a VESA VL function:
LBS16.
Some portion of the Address Bus will be floated at the
time of an address hold operation, which is signaled with
the AHOLD pin. The number of Address Bus pins to be
floated will be determined by the value of the Cache Line
Length (CLL) register (BCR18, bits 15-11) as shown in
Table 14.
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