參數(shù)資料
型號(hào)： AM79C965KCW
廠(chǎng)商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 60/220頁(yè)
文件大?。?/td> 1197K
代理商： AM79C965KCW
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AMD
P R E L I M I N A R Y
152
Am79C965
goes active if the 10BASE-T port
comes of out of “l(fā)ink fail” state.
This
LNKST pin can be used by
external circuitry to re-enable the
PCnet-32 controller and/or other
devices.
When AWAKE = “0”, the Auto-
Wake circuitry is disabled. This
bit only has meaning when the
10BASE-T network interface is
selected.
This bit is reset to ZERO by
H_RESET and is unaffected by
S_RESET or STOP.
1
ASEL
Auto Select. When set, the
PCnet-32 controller will auto-
matically select the operating
media interface port, unless the
user has selected GPSI mode
through appropriate program-
ming of the PORTSEL bits of the
Mode Register (CSR15). If GPSI
mode has not been selected and
ASEL has been set to a ONE,
then when the 10BASE-T trans-
ceiver is in the link pass state
(due to receiving valid frame data
and/or Link Test pulses or the
DLNKTST
bit
is
set),
the
10BASE-T port will be used. If
GPSI mode has not been se-
lected and ASEL has been set to
a ONE, then when the 10BASE-T
port is in the link fail state, the AUI
port will be used. Switching be-
tween the ports will not occur dur-
ing transmission, to avoid any
type of fragment generation.
When ASEL is set to ONE, Link
Beat Pulses will be transmitted
on the 10BASE-T port, regard-
less of the state of Link Status.
When ASEL is reset to ZERO,
Link Beat Pulses will only be
transmitted on the 10BASE-T
port when the PORTSEL bits of
the
Mode
Register
(CSR15)
have selected 10BASE-T as the
active port.
When ASEL is set to a ZERO,
then the selected network port
will be determined by the settings
of the PORTSEL bits of CSR15.
The ASEL bit is reset to ONE by
H_RESET and is unaffected by
S_RESET or STOP.
The network port configuration
are as follows:
ASEL
Link Status
Network
PORTSEL(1:0) (BCR2[1])
(of 10BASE-T)
Port
0X
1
0
AUI
0X
1
10BASE-T
0 0
0
X
AUI
0 1
0
X
10BASE-T
1 0
X
GPSI
1 1
X
Reserved
0
RES
Reserved location. The default
value of this bit is a ZERO. Writ-
ing a ONE to this bit has no effect
on device function. Existing driv-
ers may write a ONE to this bit,
but new drivers should write a
ZERO to this bit.
BCR4: Link Status LED
Bit
Name
Description
BCR4 controls the function(s)
that the
LNKST pin displays. Mul-
tiple functions can be simultane-
ously enabled on this LED pin.
The LED display will indicate the
logical OR of the enabled func-
tions. BCR4 defaults to Link
Status
(LNKST)
with
pulse
stretcher enabled (PSE = 1) and
is fully programmable.
The
default
setting
after
H_RESET for the
LNKST regis-
ter is 00C0h. The
LNKST register
value is unaffected by S_RESET
or STOP.
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
LEDOUT
This bit indicates the current
(non-stretched) value of the LED
output pin. A value of ONE in this
bit indicates that the OR of the
enabled signals is true.
The logical value of the LEDOUT
status signal is determined by the
settings of the individual Status
Enable bits of the LED register
(Bits 6-0).
This bit is READ only by the host,
and is unaffected by H_RESET
or S_RESET or STOP.
This bit is valid only if the network
link status is PASS.
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