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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 164/220頁 |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
48
Am79C965
whichever is more stringent. The concepts discussed in
the following sections and the basic nature of the timings
shown is applicable in a general sense to PCnet-32 con-
troller operational modes. For specific differences in
timing between modes and for examples of timing dia-
grams showing basic transfers in each of the modes,
please consult the following sections:
Am486 32-bit mode:
Bus Acquisition section
through
Slave Timing section
VESA VL-Bus mode:
VESA VL-Bus Mode Timing
section
For selection of each mode, consult the section on Con-
figuration Pins in the
Pin Description section.
Note that all timing diagrams in this document have
been drawn showing reference to two groups of address
pins: namely, A4–A31 and A2–A3,
BE0–BE3. In the
AHOLD timing diagrams, the two groups are shown
separately, because the upper address pins become
floated, while the lower address pins do not. The point of
division between the two groups of address pins will de-
pend upon the value of CLL in BCR18. In the case of Lin-
ear Burst operations, the upper address pins are shown
separately because that group does not change its
value through a single linear burst, while the lower ad-
dress pins do change value. In this case, the point of di-
vision between the two groups of address pins will
depend upon the value of LINBC in BCR18. In all other
timing diagrams, the two groups are shown separately
just to maintain consistency with the AHOLD and Linear
Burst timing diagrams. For more details, see the
AHOLD and Linear Burst Count sections.
Bus Acquisition
The PCnet-32 controller microcode (in the buffer man-
agement section) will determine when a DMA transfer
should be initiated. The first step in any PCnet-32 con-
troller bus master transfer is to acquire ownership of the
bus. This task is handled by synchronous logic within
the BIU. Bus ownership is requested with the HOLD sig-
nal and ownership is granted by the CPU (or an arbiter)
through the HLDA signal. The PCnet-32 controller addi-
tionally supplies HOLDI and HLDAO signals to allow
daisy chaining of devices through the PCnet-32 control-
ler. Priority of the HOLDI input versus the PCnet-32 con-
troller’s own internal request for bus mastership can be
set using the PRPCNET bit of BCR17. Simple bus arbi-
tration (HOLD, HLDA only) is shown in Figure 1.
Note that assertion of the STOP bit will not cause a
deassertion of the HOLD signal. Note also that a read of
the S_RESET register (I/O resource at offset 14h from
the PCnet-32 controller base I/O address) will not cause
a deassertion of the HOLD signal. Either of these ac-
tions will cause the internal master state machine logic
to cease operations, but the HOLD signal will remain ac-
tive until the HLDA signal is synchronously sampled as
asserted. Following either of the above actions, on the
next clock cycle after the HLDA signal is synchronously
sampled as asserted, the PCnet-32 controller will deas-
sert the HOLD signal. No bus master accesses will have
been performed during this brief bus ownership period.
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