參數(shù)資料
型號: AM79C965KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝: PLASTIC, QFP-160
文件頁數(shù): 163/220頁
文件大小: 1197K
代理商: AM79C965KCW
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P R E L I M I N A R Y
AMD
47
Am79C965
BASIC FUNCTIONS
System Bus Interface Function
The PCnet-32 controller is designed to operate as a Bus
Master during normal operations. Some slave accesses
to the PCnet-32 controller are required in normal opera-
tions as well. Initialization of the PCnet-32 controller is
achieved through a combination of Bus Slave accesses,
Bus Master accesses and an optional read of a serial
EEPROM that is performed by the PCnet-32 controller.
The EEPROM read operation is performed through the
microwire interface. The ISO 8802-3 (IEEE/ANSI 802.3)
Ethernet
Address
may
reside
within
the
serial
EEPROM. Some PCnet-32 controller configuration reg-
isters may also be programmed by the EEPROM read
operation.
The address PROM, on-chip board-configuration regis-
ters, and the Ethernet controller registers occupy 32
bytes of I/O space which can be located by modifying
the I/O base address register. The default base address
can be written to the EEPROM. The PCnet-32 controller
will automatically read the I/O Base Address from the
EEPROM after H_RESET, or at any time that the soft-
ware requests that the EEPROM should be read. When
no EEPROM is attached to the serial microwire inter-
face, the PCnet-32 controller detects the condition, and
enters Software Relocatable Mode. While in Software
Relocatable Mode, the PCnet-32 controller will not re-
spond to any bus accesses, but will snoop the bus for
accesses to I/O address 378h. When a successfully
executed and uninterrupted sequence of write opera-
tions is seen at this location, the PCnet-32 controller will
accept the next sequence of accesses as carrying I/O
Base Address relocation and interrupt pin programming
information. After this point, the PCnet-32 controller
will begin to respond directly to accesses directed to-
ward offsets from the newly loaded I/O Base Address.
This scheme allows for jumperless relocatable I/O
implementations.
Software Interface
The software interface to the PCnet-32 controller is di-
vided into two parts. One part is the direct access to the
I/O resources of the PCnet-32 controller. The PCnet-32
controller occupies 32 bytes of I/O space that must be-
gin on a 32-byte block boundary. The I/O Base Address
can be changed to any 32-bit quantity that begins on a
32-byte block boundary through the function of the Soft-
ware Relocatable Mode. It can also be changed to any
32-bit value that begins on a 32-byte block boundary
through the automatic EEPROM read operation that oc-
curs immediately after the H_RESET function has com-
pleted. This read operation automatically alters the I/O
Base Address of the PCnet-32 controller.
The 32-byte I/O space is used by the software to pro-
gram the PCnet-32 controller operating mode, to enable
and disable various features, to monitor operating
status and to request particular functions to be executed
by the PCnet-32 controller.
The other portion of the software interface is the descrip-
tor and buffer areas that are shared between the soft-
ware and the PCnet-32 controller during normal network
operations. The descriptor area boundaries are set by
the software and do not change during normal network
operations. There is one descriptor area for receive ac-
tivity and there is a separate area for transmit activity.
The descriptor space contains relocatable pointers to
the network packet data
and it is used to transfer packet
status from the PCnet-32 controller to the software. The
buffer areas are locations that hold packet data for
transmission or that accept packet data that has
been received.
Network Interfaces
The PCnet-32 controller can be connected to an 802.3
network via one of two network interfaces. The Attach-
ment Unit Interface (AUI) provides an ISO 8802-3
(IEEE/ANSI 802.3) compliant differential interface to a
remote
MAU
or
an
on-board
transceiver.
The
10BASE-T interface provides a twisted-pair Ethernet
port. While in auto-selection mode, the interface in use
is determined by an auto-sensing mechanism which
checks the link status on the 10BASE-T port. If there is
no active link status, then the device assumes an
AUI connection.
DETAILED FUNCTIONS
Bus Interface Unit
The bus interface unit is built of several state machines
that run synchronously to BCLK. One bus interface unit
state machine handles accesses where the PCnet-32
controller is the bus slave, and another handles ac-
cesses where the PCnet-32 controller is the bus master.
All inputs are synchronously sampled
except
ADS,
M/
IO, D/C, W/R and the A[31:5] bus when this bus is an
input to the PCnet-32 controller. All outputs are synchro-
nously generated on the rising edge of BCLK
with the
following exceptions:
LDEV is generated asynchronously.
RDY is
driven/floated on falling edges of BCLK but will
change state on rising edges of BCLK.
The following sections describe the various bus master
and bus slave operations that will be performed by the
PCnet-32 controller. The timing diagrams that are in-
cluded in these sections (
Bus Acquisition section
through
Slave Timing section) show the signals and tim-
ings of the Am486 32-bit mode of operation. The sec-
tions from
Bus Acquisition through Linear Burst DMA
Transfers show bus master operations. The Slave Tim-
ing section shows bus slave operations. Note that the
PCnet-32 controller operation in Am486 32-bit mode
represents a merger of the requirements of the VESA
VL-Bus specification and Am486 bus specification,
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