參數(shù)資料
型號： AM79C965KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁數(shù)： 53/220頁
文件大?。?/td> 1197K
代理商： AM79C965KCW
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AMD
P R E L I M I N A R Y
146
Am79C965
CSR94: Transmit Time Domain Reflectometry
Count
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-10
RES
Reserved locations. Read and
written as zero.
9-0
XMTTDR
Time Domain Reflectometry re-
flects the state of an internal
counter that counts from the start
of transmission to the occurrence
of loss of carrier. TDR is incre-
mented at a rate of 10 MHz.
Read
accessible
only
when
STOP bit is set. Write operations
are ignored. XMTTDR is cleared
by H_RESET or S_RESET.
CSR96: Bus Interface Scratch Register 0 Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
SCR0
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers. The SCR0
register is undefined until written.
Read/write accessible only when
STOP bit is set.
CSR97: Bus Interface Scratch Register 0 Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
SCR0
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers. The SCR0
register is undefined until written.
Read/write accessible only when
STOP bit is set.
CSR98: Bus Interface Scratch Register 1 Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
SCR1
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers.
Read/write accessible only when
STOP bit is set.
CSR99: Bus Interface Scratch Register 1 Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
SCR1
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers.
Read/write accessible only when
STOP bit is set.
CSR100: Bus Time-out
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0 MERRTO
This register contains the value
of the longest allowable bus la-
tency (interval between assertion
of HOLD and assertion of HLDA)
that a slave device may insert
into a PCnet-32 controller master
transfer. If this value of bus la-
tency is exceeded, then a MERR
will be indicated in CSR0, bit 11,
and an interrupt may be gener-
ated, depending upon the setting
of the MERRM bit (CSR3, bit 11)
and IENA bit (CSR0[6]).
The value in this register is inter-
preted as a number of XTAL1
÷2
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