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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 158/220頁 |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
42
Am79C965
performed by the PCnet-32 controller, except that linear
burst transfers may also be terminated with the
BRDY
signal.
RDYRTN is used to terminate slave read ac-
cesses to PCnet-32 controller I/O space.
When asserted during slave read accesses to PCnet-32
controller I/O space,
RDYRTN indicates that the bus
mastering device has seen the
RDY that was generated
by the PCnet-32 controller and has accepted the
PCnet-32 controller slave read data. Therefore,
PCnet-32 controller will hold slave read data on the bus
until it synchronously samples the
RDYRTN input as
active low. The PCnet-32 controller will
not hold
RDY
valid asserted during this time. The duration of the
RDY
pulse generated by the PCnet-32 controller will always
be a single BCLK cycle.
RDYRTN is ignored during slave write accesses to
PCnet-32 controller I/O space. Slave write accesses to
PCnet-32 controller I/O space are considered termi-
nated by the PCnet-32 controller at the end of the cycle
during which the PCnet-32 controller issues an
active
RDY.
In systems where both a
RDY and RDYRTN (or equiva-
lent) signals are provided, then
RDY must not be tied to
RDYRTN. Most systems now provide for a local device
ready input to the memory controller that is separate
from the CPU
READY signal. This second READY sig-
nal is usually labeled as
READYIN. This signal should
be connected to the PCnet-32 controller
RDY signal.
The CPU
READY signal should be connected to the
PCnet-32 controller
RDYRTN pin.
In systems where only one
READY signal is provided,
then the PCnet-32 controller
RDY output may be tied to
the PCnet-32 controller
RDYRTN input.
W/R
Write/Read Select
Input/Output
During slave accesses to the PCnet-32 controller, the
W/
R pin, along with D/C and M/IO, indicates the type of
cycle that is being performed.
During PCnet-32 controller bus master accesses, the
W/
R pin is an output.
W/
R is floated if the PCnet-32 controller is not the cur-
rent master on the local bus.
Board Interface
LED1
Output
This pin is shared with the EESK function. When operat-
ing as LED1, the function and polarity on this pin are
programmable through BCR5. The LED1 output from
the PCnet-32 controller is capable of sinking the neces-
sary 12 mA of current to drive an LED directly.
The LED1 pin is also used during EEPROM Auto-detec-
tion to determine whether or not an EEPROM is present
at the PCnet-32 controller microwire interface. At the
trailing edge of RESET, this pin is sampled to determine
the value of the EEDET bit in BCR19. A sampled HIGH
value means that an EEPROM is present, and EEDET
will be set to ONE. A sampled LOW value means that an
EEPROM is not present, and EEDET will be set to
ZERO. See the “EEPROM Auto-detection” section for
more details.
If no LED circuit is to be attached to this pin, then a
pull-up or pull-down resistor must be attached instead,
in order to resolve the EEDET setting.
LED2
Output
This pin is shared with the SRDCLK function. When
operating as LED2, the function and polarity on this pin
are programmable through BCR6. The LED2 output
from the PCnet-32 controller is capable of sinking the
necessary 12 mA of current to drive an LED directly.
This pin also selects address width for Software
Relocatable Mode. When this pin is HIGH during Soft-
ware Relocatable Mode, then the device will be pro-
grammed to use 32 bits of addressing while snooping
accesses on the bus during Software Relocatable
Mode. When this pin is LOW during Software
Relocatable Mode, then the device will be programmed
to use 24 bits of addressing while snooping accesses on
the bus during Software Relocatable Mode. The upper
8 bits of address will be assumed to match during the
snooping operation when LED2 is LOW. The 24-bit ad-
dressing mode is intended for use in systems that em-
ploy the GPSI signals. For more information on the
GPSI function see section
General Purpose Serial
Interface.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead, in
order to resolve the Software Relocatable Mode ad-
dress setting.
LEDPRE3
Output
This pin is shared with the EEDO function. When operat-
ing as LEDPRE3, the function and polarity on this pin
are programmable through BCR7. This signal is labeled
as LED “
PRE” 3 because of the multi-function nature of
this pin. If an LED circuit were directly attached to this
pin, it would create an IOL requirement that could not be
met by the serial EEPROM that would also be attached
to this pin. Therefore, if this pin is to be used as an
additional LED output while an EEPROM is used in the
system, then buffering is required between the
LEDPRE3 pin and the LED circuit. If no EEPROM is
included in the system design, then the LEDPRE3 sig-
nal may be directly connected to an LED without buffer-
ing. The LEDPRE3 output from the PCnet-32 controller
is capable of sinking the necessary 12 mA of current to
drive an LED in this case. For more details regarding
LED connection, see the section on LEDs.
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