參數(shù)資料
型號(hào)： AM79C965KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 52/220頁(yè)
文件大?。?/td> 1197K
代理商： AM79C965KCW
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P R E L I M I N A R Y
AMD
145
Am79C965
until the first PCnet-32 controller
DMA
operation.
When
the
ENTST bit in CSR4 is set, all
writes to this register will auto-
matically perform an increment
cycle.
Read/write accessible only when
STOP bit is set.
CSR85: DMA Address Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
DMABA
DMA Address Register.
This register contains the upper
16 bits of the address of system
memory for the current DMA cy-
cle. The Bus Interface Unit con-
trols the Address Register by
issuing increment commands to
increment the memory address
for sequential operations. The
DMABA register is undefined un-
til the first PCnet-32 controller
DMA
operation.
When
the
ENTST bit in CSR4 is set, all
writes to this register will auto-
matically perform an increment
cycle.
Read/write accessible only when
STOP bit is set.
CSR86: Buffer Byte Counter
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-12
RES
Reserved, Read and written with
ones.
11-0
DMABC
DMA Byte Count Register. Con-
tains a Two’s complement binary
number of the current size of the
remaining transmit or receive
buffer in bytes. This register is in-
cremented by the Bus Interface
Unit. The DMABC register is un-
defined
until
written.
When
ENTST (CSR4.15) is asserted,
all writes to this register will auto-
matically perform an increment
cycle.
Read/write accessible only when
STOP bit is set.
CSR88: Chip ID Lower
Bit
Name
Description
This register is exactly the same
as the Chip ID register in the
JTAG description.
31 - 28
Version. This 4-bit pattern is sili-
con-revision dependent.
27 - 12
Part number. The 16-bit code for
the
PCnet-32
controller
is
0010 0100 0011 0000b.
11 - 1
Manufacturer
ID.
The
11-bit
manufacturer code for AMD is
00000000001b. This code is per
the JEDEC Publication 106-A.
0
Always a logic 1.
CSR89: Chip ID Upper
Bit
Name
Description
The lower 16 bits of this register
are exactly the same as the up-
per 16 bits of the Chip ID register
in the JTAG description, which
are exactly the same as the up-
per 16 bits of CSR88.
31 - 16
Reserved locations. Read as un-
defined.
15 - 12
Version. This 4-bit pattern is sili-
con-revision dependent.
11 - 0
Upper 12 bits of the PCnet-32
controller
part
number,
i.e.
0010 0100 0011b.
CSR92: Ring Length Conversion
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RCON
Ring Length Conversion Regis-
ter. This register performs a ring
length conversion from an en-
coded value as found in the in-
itialization block to a Two’s
complement value used for inter-
nal counting. By writing bits
15-12 with an encoded ring
length, a Two’s complemented
value is read. The RCON register
is undefined until written.
Read/write accessible only when
STOP bit is set.
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